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Message-ID: <7c2242ff-f526-a305-9d4b-650427a58a9d@gmail.com>
Date: Thu, 15 Sep 2022 17:59:21 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Bo-Chen Chen <rex-bc.chen@...iatek.com>, chunkuang.hu@...nel.org,
p.zabel@...gutronix.de, airlied@...ux.ie
Cc: granquet@...libre.com, daniel@...ll.ch, jitao.shi@...iatek.com,
angelogioacchino.delregno@...labora.com, ck.hu@...iatek.com,
liangxu.xu@...iatek.com, dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH 2/3] drm/mediatek: dp: Remove unused register definitions
On 15/09/2022 09:50, Bo-Chen Chen wrote:
> Some definitions in mtk_dp_reg.h are not used, so remove these
> redundant codes.
>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 096ad6572a5e..84e38cef03c2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -153,8 +153,6 @@
> #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
> #define MTK_DP_ENC0_P0_3094 0x3094
> #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)
> -#define MTK_DP_ENC0_P0_30A0 0x30a0
> -#define DP_ENC0_30A0_MASK (BIT(7) | BIT(8) | BIT(12))
> #define MTK_DP_ENC0_P0_30A4 0x30a4
> #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)
> #define MTK_DP_ENC0_P0_30A8 0x30a8
> @@ -171,8 +169,6 @@
> #define MTK_DP_ENC0_P0_312C 0x312c
> #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
> #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
> -#define MTK_DP_ENC0_P0_3130 0x3130
> -#define MTK_DP_ENC0_P0_3138 0x3138
> #define MTK_DP_ENC0_P0_3154 0x3154
> #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)
> #define MTK_DP_ENC0_P0_3158 0x3158
> @@ -206,8 +202,6 @@
> #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)
> #define SDP_PACKET_W_DP_ENC1_P0 BIT(5)
> #define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5)
> -#define MTK_DP_ENC1_P0_328C 0x328c
> -#define VSC_DATA_RDY_VESA_DP_ENC1_P0_MASK BIT(7)
> #define MTK_DP_ENC1_P0_3300 0x3300
> #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2
> #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
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