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Message-Id: <20220921214439.1491510-4-stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 14:43:46 -0700
From: Chris Stillson <stillson@...osinc.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Guo Ren <guoren@...ux.alibaba.com>,
Greentime Hu <greentime.hu@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <keescook@...omium.org>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Oleg Nesterov <oleg@...hat.com>, Guo Ren <guoren@...nel.org>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
Chris Stillson <stillson@...osinc.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Qinglin Pan <panqinglin2020@...as.ac.cn>,
Alexandre Ghiti <alexandre.ghiti@...onical.com>,
Vincent Chen <vincent.chen@...ive.com>,
Arnd Bergmann <arnd@...db.de>,
Heiko Stuebner <heiko@...ech.de>,
Jisheng Zhang <jszhang@...nel.org>,
Dao Lu <daolu@...osinc.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Sunil V L <sunilvl@...tanamicro.com>,
Han-Kuan Chen <hankuan.chen@...ive.com>,
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Alexander Graf <graf@...zon.com>,
Ard Biesheuvel <ardb@...nel.org>,
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Catalin Marinas <catalin.marinas@....com>,
Mark Brown <broonie@...nel.org>, Will Deacon <will@...nel.org>,
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Janosch Frank <frankja@...ux.ibm.com>,
Christian Brauner <brauner@...nel.org>,
Evgenii Stepanov <eugenis@...gle.com>,
Peter Collingbourne <pcc@...gle.com>,
Eugene Syromiatnikov <esyr@...hat.com>,
Colin Cross <ccross@...gle.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Suren Baghdasaryan <surenb@...gle.com>,
Barret Rhoden <brho@...gle.com>,
Davidlohr Bueso <dave@...olabs.net>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mm@...ck.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org
Subject: [PATCH v12 04/17] riscv: Add vector feature to compile
From: Guo Ren <guoren@...ux.alibaba.com>
This patch adds a new config option which could enable assembler's
vector feature.
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Co-developed-by: Greentime Hu <greentime.hu@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
---
arch/riscv/Kconfig | 15 +++++++++++++--
arch/riscv/Makefile | 1 +
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ed66c31e4655..e294d85bfb7d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -432,7 +432,17 @@ config FPU
If you don't know what to do here, say Y.
-endmenu # "Platform type"
+config VECTOR
+ bool "VECTOR support"
+ depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000
+ default n
+ help
+ Say N here if you want to disable all vector related procedure
+ in the kernel.
+
+ If you don't know what to do here, say Y.
+
+endmenu
menu "Kernel features"
@@ -556,6 +566,7 @@ config CMDLINE_EXTEND
cases where the provided arguments are insufficient and
you don't want to or cannot modify them.
+
config CMDLINE_FORCE
bool "Always use the default kernel command string"
help
@@ -648,7 +659,7 @@ config XIP_PHYS_ADDR
be linked for and stored to. This address is dependent on your
own flash usage.
-endmenu # "Boot options"
+endmenu
config BUILTIN_DTB
bool
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 3fa8ef336822..1ec17f3d6d09 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -50,6 +50,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
+riscv-march-$(CONFIG_VECTOR) := $(riscv-march-y)v
# Newer binutils versions default to ISA spec version 20191213 which moves some
# instructions from the I extension to the Zicsr and Zifencei extensions.
--
2.25.1
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