linux-kernel - [PATCH v12 03/17] riscv: Add new csr defines related to vector extension

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220921214439.1491510-3-stillson@rivosinc.com>
Date:   Wed, 21 Sep 2022 14:43:45 -0700
From:   Chris Stillson <stillson@...osinc.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     Greentime Hu <greentime.hu@...ive.com>,
        Guo Ren <guoren@...nel.org>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Vincent Chen <vincent.chen@...ive.com>,
        Palmer Dabbelt <palmer@...osinc.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Eric Biederman <ebiederm@...ssion.com>,
        Kees Cook <keescook@...omium.org>,
        Anup Patel <anup@...infault.org>,
        Atish Patra <atishp@...shpatra.org>,
        Oleg Nesterov <oleg@...hat.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
        Mayuresh Chitale <mchitale@...tanamicro.com>,
        Chris Stillson <stillson@...osinc.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Qinglin Pan <panqinglin2020@...as.ac.cn>,
        Alexandre Ghiti <alexandre.ghiti@...onical.com>,
        Arnd Bergmann <arnd@...db.de>,
        Heiko Stuebner <heiko@...ech.de>,
        Jisheng Zhang <jszhang@...nel.org>,
        Dao Lu <daolu@...osinc.com>,
        Sunil V L <sunilvl@...tanamicro.com>,
        Han-Kuan Chen <hankuan.chen@...ive.com>,
        Li Zhengyu <lizhengyu3@...wei.com>,
        Alexander Graf <graf@...zon.com>,
        Ard Biesheuvel <ardb@...nel.org>,
        Tsukasa OI <research_trasio@....a4lg.com>,
        Yury Norov <yury.norov@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        Nicolas Saenz Julienne <nsaenzju@...hat.com>,
        Frederic Weisbecker <frederic@...nel.org>,
        Changbin Du <changbin.du@...el.com>,
        hasheddan <georgedanielmangum@...il.com>,
        Vitaly Wool <vitaly.wool@...sulko.com>,
        Myrtle Shah <gatecat@....me>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Alexey Dobriyan <adobriyan@...il.com>,
        Huacai Chen <chenhuacai@...nel.org>,
        Janosch Frank <frankja@...ux.ibm.com>,
        Christian Brauner <brauner@...nel.org>,
        Evgenii Stepanov <eugenis@...gle.com>,
        Colin Cross <ccross@...gle.com>,
        Peter Collingbourne <pcc@...gle.com>,
        Eugene Syromiatnikov <esyr@...hat.com>,
        Barret Rhoden <brho@...gle.com>,
        Suren Baghdasaryan <surenb@...gle.com>,
        Davidlohr Bueso <dave@...olabs.net>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mm@...ck.org, kvm@...r.kernel.org,
        kvm-riscv@...ts.infradead.org
Subject: [PATCH v12 03/17] riscv: Add new csr defines related to vector extension

From: Greentime Hu <greentime.hu@...ive.com>

Follow the riscv vector spec to add new csr numbers.

[guoren@...ux.alibaba.com: first porting for new vector related csr]
Acked-by: Guo Ren <guoren@...nel.org>
Co-developed-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@...ive.com>
Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Reviewed-by: Palmer Dabbelt <palmer@...osinc.com>
---
 arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0e571f6483d9..78a68f29c3ba 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
 #define SR_FS_CLEAN	_AC(0x00004000, UL)
 #define SR_FS_DIRTY	_AC(0x00006000, UL)
 
+#define SR_VS           _AC(0x00000600, UL) /* Vector Status */
+#define SR_VS_OFF       _AC(0x00000000, UL)
+#define SR_VS_INITIAL   _AC(0x00000200, UL)
+#define SR_VS_CLEAN     _AC(0x00000400, UL)
+#define SR_VS_DIRTY     _AC(0x00000600, UL)
+
 #define SR_XS		_AC(0x00018000, UL) /* Extension Status */
 #define SR_XS_OFF	_AC(0x00000000, UL)
 #define SR_XS_INITIAL	_AC(0x00008000, UL)
@@ -31,9 +37,9 @@
 #define SR_XS_DIRTY	_AC(0x00018000, UL)
 
 #ifndef CONFIG_64BIT
-#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x80000000, UL) /* FS/VS/XS dirty */
 #else
-#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
 #endif
 
 #ifdef CONFIG_64BIT
@@ -297,6 +303,12 @@
 #define CSR_MIMPID		0xf13
 #define CSR_MHARTID		0xf14
 
+#define CSR_VSTART		0x8
+#define CSR_VCSR		0xf
+#define CSR_VL			0xc20
+#define CSR_VTYPE		0xc21
+#define CSR_VLENB		0xc22
+
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE
-- 
2.25.1