linux-kernel - RE: [PATCH v4 1/6] x86/hyperv: Add HV_INVARIANT_TSC

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Message-ID: <BYAPR21MB16883BE5057ECC1BB99B4170D74E9@BYAPR21MB1688.namprd21.prod.outlook.com>
Date:   Thu, 22 Sep 2022 22:07:53 +0000
From:   "Michael Kelley (LINUX)" <mikelley@...rosoft.com>
To:     Vitaly Kuznetsov <vkuznets@...hat.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>
CC:     Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Maxim Levitsky <mlevitsk@...hat.com>,
        "linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 1/6] x86/hyperv: Add HV_INVARIANT_TSC_EXPOSED define

From: Vitaly Kuznetsov <vkuznets@...hat.com> Sent: Thursday, September 22, 2022 7:37 AM
> 
> Avoid open coding BIT(0) of HV_X64_MSR_TSC_INVARIANT_CONTROL by adding
> a dedicated define. While there's only one user at this moment, the
> upcoming KVM implementation of Hyper-V Invariant TSC feature will need
> to use it as well.
> 
> Signed-off-by: Vitaly Kuznetsov <vkuznets@...hat.com>
> ---
>  arch/x86/include/asm/hyperv-tlfs.h | 3 +++
>  arch/x86/kernel/cpu/mshyperv.c     | 2 +-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
> index 3089ec352743..4849f879948d 100644
> --- a/arch/x86/include/asm/hyperv-tlfs.h
> +++ b/arch/x86/include/asm/hyperv-tlfs.h
> @@ -253,6 +253,9 @@ enum hv_isolation_type {
>  /* TSC invariant control */
>  #define HV_X64_MSR_TSC_INVARIANT_CONTROL	0x40000118
> 
> +/* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
> +#define HV_INVARIANT_TSC_EXPOSED		BIT_ULL(0)

Nit:  This name sounds like a value that is read from some register,
to find out if an Invariant TSC is exposed.  But it's actually a value that
is written to make something happen.  So my brain wants to name it
something more like HV_EXPOSE_INVARIANT_TSC.   Not a big
enough issue to respin for, but if you do respin then maybe change
it.

> +
>  /* Register name aliases for temporary compatibility */
>  #define HV_X64_MSR_STIMER0_COUNT	HV_REGISTER_STIMER0_COUNT
>  #define HV_X64_MSR_STIMER0_CONFIG	HV_REGISTER_STIMER0_CONFIG
> diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c
> index 831613959a92..3716c358da98 100644
> --- a/arch/x86/kernel/cpu/mshyperv.c
> +++ b/arch/x86/kernel/cpu/mshyperv.c
> @@ -388,7 +388,7 @@ static void __init ms_hyperv_init_platform(void)
>  		 * setting of this MSR bit should happen before init_intel()
>  		 * is called.
>  		 */
> -		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
> +		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_INVARIANT_TSC_EXPOSED);
>  		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
>  	}
> 
> --
> 2.37.3

Reviewed-by: Michael Kelley <mikelley@...rosoft.com>