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Date: Thu, 22 Sep 2022 14:24:28 +0800
From: Rahul Tanwar <rtanwar@...linear.com>
To: <sboyd@...nel.org>, <mturquette@...libre.com>,
<linux-clk@...r.kernel.org>
CC: <linux-kernel@...r.kernel.org>, <linux-lgm-soc@...linear.com>,
"Rahul Tanwar" <rtanwar@...linear.com>
Subject: [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change
One of the clock entry "dcl" clk's rate can only be changed by
changing its parent's clock rate. But it was missing to have
CLK_SET_RATE_PARENT flag as enabled.
Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to
allow its clk rate to be changed via its parent's clk.
Signed-off-by: Rahul Tanwar <rtanwar@...linear.com>
---
drivers/clk/x86/clk-lgm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c
index e312af42e97a..34e16ea90596 100644
--- a/drivers/clk/x86/clk-lgm.c
+++ b/drivers/clk/x86/clk-lgm.c
@@ -255,7 +255,7 @@ static const struct lgm_clk_branch lgm_branch_clks[] = {
LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
- LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
+ LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
25, 3, 0, 0, 0, 0, dcl_div),
LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
0, 1, CLK_MUX_ROUND_CLOSEST, 0),
--
2.17.1
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