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Message-ID: <CAGXv+5GJrjxG0pEGqseEacz_KFCRhWJSiLoiwuwwUTaSeO0RBg@mail.gmail.com>
Date:   Mon, 26 Sep 2022 13:09:24 +0800
From:   Chen-Yu Tsai <wenst@...omium.org>
To:     Guillaume Ranquet <granquet@...libre.com>
Cc:     Vinod Koul <vkoul@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        David Airlie <airlied@...ux.ie>,
        Rob Herring <robh+dt@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Daniel Vetter <daniel@...ll.ch>,
        Chunfeng Yun <chunfeng.yun@...iatek.com>,
        CK Hu <ck.hu@...iatek.com>, Jitao shi <jitao.shi@...iatek.com>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        linux-mediatek@...ts.infradead.org,
        dri-devel@...ts.freedesktop.org,
        Pablo Sun <pablo.sun@...iatek.com>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Mattijs Korpershoek <mkorpershoek@...libre.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-phy@...ts.infradead.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v1 02/17] clk: mediatek: add VDOSYS1 clock

On Tue, Sep 20, 2022 at 12:59 AM Guillaume Ranquet
<granquet@...libre.com> wrote:
>
> From: Pablo Sun <pablo.sun@...iatek.com>
>
> Add the clock gate definition for the DPI1 hardware
> in VDOSYS1.
>
> The parent clock "hdmi_txpll" is already defined in
> `mt8195.dtsi`.
>
> Signed-off-by: Pablo Sun <pablo.sun@...iatek.com>
> Signed-off-by: Guillaume Ranquet <granquet@...libre.com>

Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>

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