linux-kernel - Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device Tree

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Message-ID: <20220926122318.qmt4dnes7caua333@pali>
Date:   Mon, 26 Sep 2022 14:23:18 +0200
From:   Pali Rohár <pali@...nel.org>
To:     Elad Nachman <enachman@...vell.com>
Cc:     maukka@....kapsi.fi, Andrew Lunn <andrew@...n.ch>,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        arnd@...db.de, olof@...om.net, sebastian.hesselbarth@...il.com,
        gregory.clement@...tlin.com, linux@...linux.org.uk,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] ARM: orion5x: Add D-Link DNS-323 based on Device
 Tree

Hello Elad! I hope that would not bothering you. We are doing here
cleanup of kernel code for older Marvell SoCs (Orion) and there one
unknown thing about 88F5181's 0x10008 register. See below.

On Monday 26 September 2022 14:56:48 maukka@....kapsi.fi wrote:
> On 23.9.2022 21:02, Pali Rohár wrote:
> > On Friday 23 September 2022 14:12:24 Andrew Lunn wrote:
> > > > > > +	if (of_machine_is_compatible("dlink,dns323a1")) {
> > > > > > +		writel(0, MPP_DEV_CTRL);		/* DEV_D[31:16] */
> > > > >
> > > > > I spotted this in dns323-setup.c as well. Do you have any idea what it
> > > > > does?
> > > > >
> > > >
> > > > No idea. I have tried to replicate what was in dns323-setup.c as exactly as
> > > > possible.
> > > > I can try to leave it out and see if anything changes.
> > > 
> > > It is best to keep what we don't understand. It will be there for a
> > > reason.
> > > 
> > > 	Andrew
> > 
> > Hello! I tried to index all publicly available Marvell SoC
> > documentations into kernel documentation subfolder:
> > https://docs.kernel.org/arm/marvell.html
> > 
> > For Orion there is linked Datasheet and User Manual, so you could try to
> > find in those documents that mentioned register and check what it is
> > doing.
> 
> MPP_DEV_CTRL refers to register at address 0x10008. According to the 88F5152
> user manual it's
> 'Device Multiplex Control Register' Offset: 0x10008.
> 
> Bits    Field     Type/InitVal     Description
> [31:0]  Reserved  RES 0x03FF0000   Reserved. NOTE: Must be 0x03FF0000'.
> 
> DEV_D[31:16] receives no hits in the documentation, only to DEV_D[15:0] are
> referred.

In linked public document I found same thing. Register is for 88F5182
reserved. (You have typo in comment, it is 88F5182, not *52).

> Maybe 88F5151 is different, hard to say.

I have feeling that for 88F5181 it is not reserved and has to be
configured correctly. (Also typo in your comment, it is 88F5181, not *51).
But I have not found any copy of 88F5181 user manual document on internet.

In past 88F518x and 88F528x documents and user manuals were available
publicly on Marvell website, visible from web archive:
https://web.archive.org/web/20080607215437/http://www.marvell.com/products/media/index.jsp

But Marvell deleted these documents from their public website and for
kernel developers they are now probably lost. I do not know about any
other backups.

Elad, could you please help us? Do you have access to functional
specifications / user manuals for 88F518x and 88F528x or have
information how kernel developers can get access to those documents?
Hopefully they were not totally lost. We just need explanation for
register 'Device Multiplex Control Register' Offset: 0x10008.