| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220926150750.GF101994@thinkpad>
Date: Mon, 26 Sep 2022 20:37:50 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Asutosh Das <quic_asutoshd@...cinc.com>
Cc: quic_nguyenb@...cinc.com, quic_xiaosenh@...cinc.com,
quic_cang@...cinc.com, quic_nitirawa@...cinc.com,
quic_rampraka@...cinc.com, quic_richardp@...cinc.com,
stanley.chu@...iatek.com, adrian.hunter@...el.com,
bvanassche@....org, avri.altman@....com, beanhuo@...ron.com,
martin.petersen@...cle.com, linux-scsi@...r.kernel.org,
Alim Akhtar <alim.akhtar@...sung.com>,
"James E.J. Bottomley" <jejb@...ux.ibm.com>,
Matthias Brugger <matthias.bgg@...il.com>,
open list <linux-kernel@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-arm-kernel@...ts.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH v1 05/16] ufs: core: mcq: Configure resource regions
On Thu, Sep 22, 2022 at 06:05:12PM -0700, Asutosh Das wrote:
> Define the mcq resources and add support to ioremap
> the resource regions.
>
> Co-developed-by: Can Guo <quic_cang@...cinc.com>
> Signed-off-by: Can Guo <quic_cang@...cinc.com>
> Signed-off-by: Asutosh Das <quic_asutoshd@...cinc.com>
> ---
> drivers/ufs/core/ufs-mcq.c | 100 ++++++++++++++++++++++++++++++++++++++++++++-
> include/ufs/ufshcd.h | 28 +++++++++++++
> 2 files changed, 127 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c
> index 934556f..e5cc7ab 100644
> --- a/drivers/ufs/core/ufs-mcq.c
> +++ b/drivers/ufs/core/ufs-mcq.c
> @@ -17,6 +17,12 @@
> #define UFS_MCQ_MIN_READ_QUEUES 0
> #define UFS_MCQ_MIN_POLL_QUEUES 0
>
> +#define MCQ_QCFGPTR_MASK GENMASK(7, 0)
> +#define MCQ_QCFGPTR_UNIT 0x200
> +#define MCQ_SQATTR_OFFSET(c) \
> + ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
> +#define MCQ_QCFG_SIZE 0x40
> +
> static unsigned int dev_cmd_queue = 1;
>
> static int rw_queue_count_set(const char *val, const struct kernel_param *kp)
> @@ -85,6 +91,96 @@ module_param_cb(poll_queues, &poll_queue_count_ops, &poll_queues, 0644);
> MODULE_PARM_DESC(poll_queues,
> "Number of poll queues used for r/w. Default value is 1");
>
> +/* Resources */
> +static const struct ufshcd_res_info_t ufshcd_res_info[RES_MAX] = {
> + {.name = "ufs_mem", .resource = NULL, .base = NULL},
> + {.name = "mcq", .resource = NULL, .base = NULL},
> + /* Submission Queue DAO */
> + {.name = "mcq_sqd", .resource = NULL, .base = NULL},
> + /* Submission Queue Interrupt Status */
> + {.name = "mcq_sqis", .resource = NULL, .base = NULL},
> + /* Completion Queue DAO */
> + {.name = "mcq_cqd", .resource = NULL, .base = NULL},
> + /* Completion Queue Interrupt Status */
> + {.name = "mcq_cqis", .resource = NULL, .base = NULL},
> + /* MCQ vendor specific */
> + {.name = "mcq_vs", .resource = NULL, .base = NULL},
> +};
> +
> +static int ufshcd_mcq_config_resource(struct ufs_hba *hba)
> +{
> + struct platform_device *pdev = to_platform_device(hba->dev);
> + struct ufshcd_res_info_t *res;
> + struct resource *res_mem, *res_mcq;
> + int i, ret = 0;
> +
> + memcpy(hba->res, ufshcd_res_info, sizeof(ufshcd_res_info));
> +
> + for (i = 0; i < RES_MAX; i++) {
> + res = &hba->res[i];
> + res->resource = platform_get_resource_byname(pdev,
> + IORESOURCE_MEM,
> + res->name);
> + if (!res->resource) {
> + dev_info(hba->dev, "Resource %s not provided\n", res->name);
This is an error if below condition gets satisfied.
> + if (i == RES_MEM)
> + return -ENOMEM;
> + continue;
> + } else if (i == RES_MEM) {
> + res_mem = res->resource;
> + res->base = hba->mmio_base;
> + continue;
> + }
> +
> + res->base = devm_ioremap_resource(hba->dev, res->resource);
> + if (IS_ERR(res->base)) {
> + dev_err(hba->dev, "Failed to map res %s, err=%d\n",
> + res->name, (int)PTR_ERR(res->base));
> + res->base = NULL;
> + ret = PTR_ERR(res->base);
> + return ret;
> + }
> + }
> +
> + res = &hba->res[RES_MCQ];
> + /* MCQ resource provided in DT */
Perhaps move the comment above and use, "Bail out if MCQ resource is provided by
the platform".
> + if (res->base)
> + goto out;
> +
> + /* Manually allocate MCQ resource */
/* Manually allocate "mcq" resource from "ufs_mem" */
> + res_mcq = res->resource;
> + res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
> + if (!res_mcq) {
> + dev_err(hba->dev, "Failed to alloate MCQ resource\n");
allocate
> + return ret;
> + }
> +
> + res_mcq->start = res_mem->start +
> + MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
> + res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
> + res_mcq->flags = res_mem->flags;
> + res_mcq->name = "mcq";
> +
> + ret = insert_resource(&iomem_resource, res_mcq);
> + if (ret) {
> + dev_err(hba->dev, "Failed to insert MCQ resource %d\n", ret);
> + return ret;
> + }
> +
> + res->base = devm_ioremap_resource(hba->dev, res_mcq);
> + if (IS_ERR(res->base)) {
> + dev_err(hba->dev, "Map MCQ registers failed, err=%d\n",
"MCQ registers mapping failed, err=%d"
> + (int)PTR_ERR(res->base));
> + ret = PTR_ERR(res->base);
> + res->base = NULL;
> + return ret;
> + }
> +
> +out:
> + hba->mcq_base = res->base;
> + return 0;
> +}
> +
> static int ufshcd_mcq_config_nr_queues(struct ufs_hba *hba)
> {
> int i, rem;
> @@ -126,7 +222,9 @@ int ufshcd_mcq_init(struct ufs_hba *hba)
> int ret;
>
> ret = ufshcd_mcq_config_nr_queues(hba);
> -
> + if (ret)
> + return ret;
Newline
> + ret = ufshcd_mcq_config_resource(hba);
> return ret;
> }
>
> diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
> index 298e103..54d742a 100644
> --- a/include/ufs/ufshcd.h
> +++ b/include/ufs/ufshcd.h
> @@ -720,6 +720,30 @@ struct ufs_hba_monitor {
> };
>
> /**
> + * struct ufshcd_res_info_t - MCQ related resource regions
> + *
> + * @name: resource name
> + * @resource: pointer to resource region
> + * @base: register base address
> + */
> +struct ufshcd_res_info_t {
> + const char *name;
> + struct resource *resource;
> + void __iomem *base;
> +};
> +
> +enum ufshcd_res {
> + RES_MEM,
RES_UFS since the resource name is "ufs_mem"?
Thanks,
Mani
> + RES_MCQ,
> + RES_MCQ_SQD,
> + RES_MCQ_SQIS,
> + RES_MCQ_CQD,
> + RES_MCQ_CQIS,
> + RES_MCQ_VS,
> + RES_MAX,
> +};
> +
> +/**
> * struct ufs_hba - per adapter private structure
> * @mmio_base: UFSHCI base register address
> * @ucdl_base_addr: UFS Command Descriptor base address
> @@ -829,6 +853,8 @@ struct ufs_hba_monitor {
> * @mcq_sup: is mcq supported by UFSHC
> * @nr_hw_queues: number of hardware queues configured
> * @nr_queues: number of Queues of different queue types
> + * @res: array of resource info of MCQ registers
> + * @mcq_base: Multi circular queue registers base address
> */
> struct ufs_hba {
> void __iomem *mmio_base;
> @@ -981,6 +1007,8 @@ struct ufs_hba {
> bool mcq_sup;
> unsigned int nr_hw_queues;
> unsigned int nr_queues[HCTX_MAX_TYPES];
> + struct ufshcd_res_info_t res[RES_MAX];
> + void __iomem *mcq_base;
> };
>
> static inline bool is_mcq_supported(struct ufs_hba *hba)
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
Powered by blists - more mailing lists