linux-kernel - Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver

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Message-ID: <MN2PR19MB3693EEC08EAC5370F1D195FBB1579@MN2PR19MB3693.namprd19.prod.outlook.com>
Date:   Thu, 29 Sep 2022 05:45:59 +0000
From:   Rahul Tanwar <rtanwar@...linear.com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@...linear.com>,
        Yi xin Zhu <yzhu@...linear.com>
Subject: Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from
 clk driver

On 29/9/2022 8:17 am, Stephen Boyd wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> Quoting Rahul Tanwar (2022-09-21 23:24:26)
>> In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled
>> from EPU (power management IP) in certain power saving modes. If gate
>> clocks are allowed to be enabled/disabled from CGU clk driver, then
>> there arises a conflict where in case clk driver disables a gate clk,
>> and then EPU tries to disable the same gate clk, then it will hang
>> polling for the clk gated successful status.
> 
> Is there any point in registering these clks when they're not supposed
> to be controlled from Linux?


As mentioned in the full commit log, only reason to register these clks 
is to be backward compatible with older versions of similar SoC's which 
reuse the same clk CGU IP but do not use same power management IP. Such 
older SoCs also use the same clk driver and for them these clks are 
required to be controlled by clk ops from Linux.

Thanks,
Rahul


> 
>