linux-kernel - Re: [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <MN2PR19MB36932AE7D8804943B14CE74BB1579@MN2PR19MB3693.namprd19.prod.outlook.com>
Date:   Thu, 29 Sep 2022 06:10:10 +0000
From:   Rahul Tanwar <rtanwar@...linear.com>
To:     Stephen Boyd <sboyd@...nel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@...linear.com>,
        Yi xin Zhu <yzhu@...linear.com>
Subject: Re: [PATCH RESEND v2 4/5] clk: mxl: Add validation for register
 reads/writes

On 29/9/2022 8:20 am, Stephen Boyd wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> Quoting Rahul Tanwar (2022-09-21 23:24:27)
>> Some clocks support parent clock dividers but they do not
>> support clock gating (clk enable/disable). Such types of
>> clocks might call API's for get/set_reg_val routines with
>> width as 0 during clk_prepare_enable() call. Handle such
>> cases by first validating width during clk_prepare_enable()
>> while still supporting clk_set_rate() correctly.
>>
>> Signed-off-by: Rahul Tanwar <rtanwar@...linear.com>
>> ---
>>   drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++----
>>   1 file changed, 26 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
>> index 73ce84345f81..46daf9ebd6c9 100644
>> --- a/drivers/clk/x86/clk-cgu.h
>> +++ b/drivers/clk/x86/clk-cgu.h
>> @@ -299,29 +299,51 @@ struct lgm_clk_branch {
>>   static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
>>                                     u8 shift, u8 width, u32 set_val)
>>   {
>> -       u32 mask = (GENMASK(width - 1, 0) << shift);
>> +       u32 mask;
>>
>> +       /*
>> +        * Some clocks support parent clock dividers but they do not
>> +        * support clock gating (clk enable/disable). Such types of
>> +        * clocks might call this function with width as 0 during
>> +        * clk_prepare_enable() call. Handle such cases by not doing
>> +        * anything during clk_prepare_enable() but handle clk_set_rate()
>> +        * correctly
>> +        */
>> +       if (!width)
>> +               return;
> 
> Why are the clk_ops assigned in a way that makes the code get here? Why
> can't we have different clk_ops, or not register the clks at all, when
> the hardware can't be written?


The hardware can actually be written for such clks but only for 
clk_set_rate() op for setting the clk rate. Just that hardware does not 
provide any way to enable/disable such clks.

Alternative way to handle such clks could be that the clk consumer does
not invoke clk_prepare_enable() before invoking clk_set_rate(). But we
want to avoid making changes in the clk consumer code to keep it 
standard. And handle it here by just validating the width parameter.

Thanks,
Rahul


> 
>> +
>> +       mask = (GENMASK(width - 1, 0) << shift);
>>          regmap_update_bits(membase, reg, mask, set_val << shift);
> 
>