linux-kernel - Re: [PATCH v3 02/15] perf/x86/amd: Add IBS OP

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Date:   Fri, 30 Sep 2022 11:46:55 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Namhyung Kim <namhyung@...nel.org>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Jiri Olsa <jolsa@...nel.org>,
        Stephane Eranian <eranian@...gle.com>,
        Ian Rogers <irogers@...gle.com>, Joe Mario <jmario@...hat.com>,
        Leo Yan <leo.yan@...aro.org>, alisaidi@...zon.com,
        Andi Kleen <ak@...ux.intel.com>,
        Kan Liang <kan.liang@...ux.intel.com>,
        dave.hansen@...ux.intel.com, "H. Peter Anvin" <hpa@...or.com>,
        Ingo Molnar <mingo@...hat.com>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>, x86@...nel.org,
        linux-perf-users <linux-perf-users@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Sandipan Das <sandipan.das@....com>, ananth.narayan@....com,
        Kim Phillips <kim.phillips@....com>, santosh.shukla@....com,
        Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH v3 02/15] perf/x86/amd: Add IBS OP_DATA2 DataSrc bit
 definitions

>>>> +/* IBS_OP_DATA2 DataSrc */
>>>> +#define IBS_DATA_SRC_LOC_CACHE                  2
>>>> +#define IBS_DATA_SRC_DRAM                       3
>>>> +#define IBS_DATA_SRC_REM_CACHE                  4
>>>> +#define IBS_DATA_SRC_IO                                 7
>>>> +
>>>> +/* IBS_OP_DATA2 DataSrc Extension */
>>>> +#define IBS_DATA_SRC_EXT_LOC_CACHE              1
>>>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE                 2
>>>> +#define IBS_DATA_SRC_EXT_DRAM                   3
>>>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE          5
>>>
>>> Is 4 undefined intentionally?
>>
>> Yes, Here is the snippet from PPR (Processor Programming Reference) doc:
>>
>>   Values | Description
>>   ---------------------------------------------------------------------
>>   0h     | No valid status.
>>   1h     | Local L3 or other L1/L2 in CCX.
>>   2h     | Another CCX cache in the same NUMA node.
>>   3h     | DRAM.
>>   4h     | Reserved.
>>   5h     | Another CCX cache in a different NUMA node.
>>   6h     | DRAM address map with "long latency" bit set.
>>   7h     | MMIO/Config/PCI/APIC.
>>   8h     | Extension Memory (S-Link, GenZ, etc - identified by the CS
>>          | target and/or address map at DF's choice).
>>   9h-Bh  | Reserved.
>>   Ch     | Peer Agent Memory.
>>   Dh-1Fh | Reserved.
> 
> Thanks for sharing it.  It's a bit confusing since it was available before.

Right, these bit definitions have changed in Zen4.

> 
> Anyway, is the PPR for Zen4 publicly available now?

Sadly, no. But it's in progress.

Thanks,
Ravi