linux-kernel - Re: [PATCH v3 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents

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Message-ID: <5d8af9a1-3afc-bd69-8f34-164284a452c2@collabora.com>
Date:   Fri, 30 Sep 2022 10:29:36 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     MandyJH Liu (劉人僖) 
        <MandyJH.Liu@...iatek.com>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>
Cc:     "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "wenst@...omium.org" <wenst@...omium.org>,
        "jose.exposito89@...il.com" <jose.exposito89@...il.com>,
        "drinkcat@...omium.org" <drinkcat@...omium.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        Chun-Jie Chen (陳浚桀) 
        <Chun-Jie.Chen@...iatek.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Miles Chen (陳民樺) 
        <Miles.Chen@...iatek.com>,
        Weiyi Lu (呂威儀) <Weiyi.Lu@...iatek.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        Rex-BC Chen (陳柏辰) 
        <Rex-BC.Chen@...iatek.com>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "nfraprado@...labora.com" <nfraprado@...labora.com>
Subject: Re: [PATCH v3 08/10] clk: mediatek: clk-mt8195-topckgen: Drop
 univplls from mfg mux parents

Il 30/09/22 07:59, MandyJH Liu (劉人僖) ha scritto:
> On Tue, 2022-09-27 at 12:11 +0200, AngeloGioacchino Del Regno wrote:
>> These PLLs are conflicting with GPU rates that can be generated by
>> the GPU-dedicated MFGPLL and would require a special clock handler
>> to be used, for very little and ignorable power consumption benefits.
>> Also, we're in any case unable to set the rate of these PLLs to
>> something else that is sensible for this task, so simply drop them:
>> this will make the GPU to be clocked exclusively from MFGPLL for
>> "fast" rates, while still achieving the right "safe" rate during
>> PLL frequency locking.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@...labora.com>
>> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
>> ---
>>   drivers/clk/mediatek/clk-mt8195-topckgen.c | 9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> b/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> index 4dde23bece66..8cbab5ca2e58 100644
>> --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> @@ -298,11 +298,14 @@ static const char * const ipu_if_parents[] = {
>>   	"mmpll_d4"
>>   };
>>   
>> +/*
>> + * MFG can be also parented to "univpll_d6" and "univpll_d7":
>> + * these have been removed from the parents list to let us
>> + * achieve GPU DVFS without any special clock handlers.
>> + */
>>   static const char * const mfg_parents[] = {
>>   	"clk26m",
>> -	"mainpll_d5_d2",
>> -	"univpll_d6",
>> -	"univpll_d7"
>> +	"mainpll_d5_d2"
>>   };
>>   
>>   static const char * const camtg_parents[] = {
> There might be a problem here. Since the univpll_d6 and univpll_d7 are
> available parents in hardware design and they can be selected other
> than kernel stage, like bootloader, the clk tree listed in clk_summary
> cannot show the real parent-child relationship in such case.

I agree about that, but the clock framework will change the parent to
the "best parent" in that case... this was done to avoid writing complicated
custom clock ops just for that one.

This issue is present only on MT8195, so it can be safely solved this way,
at least for now.

Should this become a thing on another couple SoCs, it'll then make sense
to write custom clock ops just for the MFG.

Regards,
Angelo