linux-kernel - Re: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver

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Date:   Fri, 30 Sep 2022 09:28:57 +0100
From:   Ahmad Fatoum <a.fatoum@...gutronix.de>
To:     Richard Zhu <hongxing.zhu@....com>, vkoul@...nel.org,
        p.zabel@...gutronix.de, l.stach@...gutronix.de,
        bhelgaas@...gle.com, lorenzo.pieralisi@....com, robh@...nel.org,
        shawnguo@...nel.org, alexander.stein@...tq-group.com,
        marex@...x.de, richard.leitner@...ux.dev
Cc:     devicetree@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-imx@....com,
        kernel@...gutronix.de, linux-phy@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe
 PHY driver

On 29.09.22 09:37, Richard Zhu wrote:
> To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> driver.
> - Use gpr compatible string to avoid the codes duplications when add
>   another platform PCIe PHY support.
> - Re-orange the codes to let it more flexible and easy to expand.

Re-arrange

> No functions changes basicly.

No functional change.

> 
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
> Tested-by: Marek Vasut <marex@...x.de>
> Tested-by: Richard Leitner <richard.leitner@...data.com>
> Tested-by: Alexander Stein <alexander.stein@...tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@...gutronix.de>
> ---
>  drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106 +++++++++++++--------
>  1 file changed, 66 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index 2377ed307b53..59b46a4ae069 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,7 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
>  #include <linux/module.h>
> +#include <linux/of_device.h>
>  #include <linux/phy/phy.h>
>  #include <linux/platform_device.h>
>  #include <linux/regmap.h>
> @@ -45,6 +46,15 @@
>  #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
>  #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
>  
> +enum imx8_pcie_phy_type {
> +	IMX8MM,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> +	enum		imx8_pcie_phy_type variant;

Better do indentation on the member name.

> +	const char	*gpr;
> +};
> +
>  struct imx8_pcie_phy {
>  	void __iomem		*base;
>  	struct clk		*clk;
> @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
>  	u32			tx_deemph_gen1;
>  	u32			tx_deemph_gen2;
>  	bool			clkreq_unused;
> +	const struct imx8_pcie_phy_drvdata	*drvdata;
>  };
>  
>  static int imx8_pcie_phy_init(struct phy *phy)
> @@ -66,31 +77,17 @@ static int imx8_pcie_phy_init(struct phy *phy)
>  	reset_control_assert(imx8_phy->reset);
>  
>  	pad_mode = imx8_phy->refclk_pad_mode;
> -	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> -			   imx8_phy->clkreq_unused ?
> -			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_AUX_EN,
> -			   IMX8MM_GPR_PCIE_AUX_EN);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
> -			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> -			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
> -			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
> -	usleep_range(100, 200);
> -
> -	/* Do the PHY common block reset */
> -	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> -			   IMX8MM_GPR_PCIE_CMN_RST,
> -			   IMX8MM_GPR_PCIE_CMN_RST);
> -	usleep_range(200, 500);
> +	switch (imx8_phy->drvdata->variant) {
> +	case IMX8MM:
> +		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
> +		if (imx8_phy->tx_deemph_gen1)
> +			writel(imx8_phy->tx_deemph_gen1,
> +			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
> +		if (imx8_phy->tx_deemph_gen2)
> +			writel(imx8_phy->tx_deemph_gen2,
> +			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
> +		break;
> +	}

If you say no functional change intended, I'd expect that register
writes happen in the same sequence. It might be ok, that you do
this tuning here, but I think it warrants a mention in the commit
message why it's ok.


Looks good otherwise. With nitpicks addressed:

Reviewed-by: Ahmad Fatoum <a.fatoum@...gutronix.de>


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