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Message-ID: <bf4ec1cb-49a4-f5cd-8fd0-c70b287180c0@linux.ibm.com>
Date: Fri, 30 Sep 2022 16:18:15 +0530
From: kajoljain <kjain@...ux.ibm.com>
To: Ravi Bangoria <ravi.bangoria@....com>, peterz@...radead.org,
acme@...nel.org
Cc: jolsa@...nel.org, namhyung@...nel.org, eranian@...gle.com,
irogers@...gle.com, jmario@...hat.com, leo.yan@...aro.org,
alisaidi@...zon.com, ak@...ux.intel.com, kan.liang@...ux.intel.com,
dave.hansen@...ux.intel.com, hpa@...or.com, mingo@...hat.com,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
tglx@...utronix.de, bp@...en8.de, x86@...nel.org,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
sandipan.das@....com, ananth.narayan@....com, kim.phillips@....com,
santosh.shukla@....com
Subject: Re: [PATCH v3 01/15] perf/mem: Introduce
PERF_MEM_LVLNUM_{EXTN_MEM|IO}
On 9/28/22 15:27, Ravi Bangoria wrote:
> PERF_MEM_LVLNUM_EXTN_MEM which can be used to indicate accesses to
> extension memory like CXL etc. PERF_MEM_LVL_IO can be used for IO
> accesses but it can not distinguish between local and remote IO.
> Introduce new field PERF_MEM_LVLNUM_IO which can be clubbed with
> PERF_MEM_REMOTE_REMOTE to indicate Remote IO accesses.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
> ---
> include/uapi/linux/perf_event.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index e639c74cf5fb..4ae3c249f675 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1336,7 +1336,9 @@ union perf_mem_data_src {
> #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
> #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
> #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
> -/* 5-0xa available */
> +/* 5-0x8 available */
> +#define PERF_MEM_LVLNUM_EXTN_MEM 0x09 /* Extension memory */
Hi Ravi,
Here we are adding entry explicitly for accesses to Extension memory
like CXL. In future if we want to extend it for cache or other accesses
, we again need to add new entries.
Can we rather add single entry say PERF_MEM_LVLNUM_EXTN and further can
use reserved bits to specify memory/cache?
Thanks,
Kajol Jain
> +#define PERF_MEM_LVLNUM_IO 0x0a /* I/O */
> #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
> #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
> #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
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