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Message-ID: <Yzgb0GzpLsV3RJyk@spud>
Date: Sat, 1 Oct 2022 11:52:00 +0100
From: Conor Dooley <conor@...nel.org>
To: Hal Feng <hal.feng@...ux.starfivetech.com>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Linus Walleij <linus.walleij@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree
On Fri, Sep 30, 2022 at 03:49:14PM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@...il.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by
> StarFive Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> Signed-off-by: Jianlong Huang <jianlong.huang@...rfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@...ux.starfivetech.com>
There's little point reviewing this dt since there's a load of issues
that you can trivially find by running dtbs_check/dt_binding_check, but
this SoB change is wrong - if Emil wrote the patch, then Jianlong's SoB
is either redundant or should be accompanied by a Co-developed-by tag.
Ditto for patch 28/30 "RISC-V: Add StarFive JH7110 VisionFive2 board
device tree".
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 449 +++++++++++++++++++++++
> 1 file changed, 449 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..46f418d4198a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +
> + osc: osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + clk_rtc: clk_rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
I assume, given osc has it's frequency set in the board dts, that these
are all oscillators on the SoC?
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <49152000>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <49152000>;
> + };
> + syscrg: syscrg@...20000 {
The generic node name for syscons is just "syscon" afaik.
> + compatible = "syscon", "simple-mfd";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> +
> + aoncrg: aoncrg@...00000 {
Again, syscon as the node name?
> + compatible = "syscon", "simple-mfd";
> + reg = <0x0 0x17000000 0x0 0x10000>;
> +
> + gpio: gpio@...40000 {
Someone else (Krzysztof maybe?) should comment, but is "pinctrl" not the
genric node name for pinctrl nodes?
Thanks,
Conor.
> + compatible = "starfive,jh7110-sys-pinctrl";
> + reg = <0x0 0x13040000 0x0 0x10000>;
> + reg-names = "control";
> + clocks = <&syscrg_clk JH7110_SYSCLK_IOMUX>;
> + resets = <&syscrg_rst JH7110_SYSRST_IOMUX>;
> + interrupts = <86>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <64>;
> + };
> +
> + gpioa: gpio@...20000 {
> + compatible = "starfive,jh7110-aon-pinctrl";
> + reg = <0x0 0x17020000 0x0 0x10000>;
> + reg-names = "control";
> + resets = <&aoncrg_rst JH7110_AONRST_AON_IOMUX>;
> + interrupts = <85>;
> + interrupt-controller;
> + #gpio-cells = <2>;
> + ngpios = <4>;
> + };
> +
> + uart0: serial@...00000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART0_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART0_CORE>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart1: serial@...10000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10010000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART1_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART1_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART1_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART1_CORE>;
> + interrupts = <33>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart2: serial@...20000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART2_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART2_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART2_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART2_CORE>;
> + interrupts = <34>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@...00000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12000000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART3_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART3_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART3_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART3_CORE>;
> + interrupts = <45>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart4: serial@...10000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12010000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART4_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART4_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART4_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART4_CORE>;
> + interrupts = <46>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + uart5: serial@...20000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x12020000 0x0 0x10000>;
> + clocks = <&syscrg_clk JH7110_SYSCLK_UART5_CORE>,
> + <&syscrg_clk JH7110_SYSCLK_UART5_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg_rst JH7110_SYSRST_UART5_APB>,
> + <&syscrg_rst JH7110_SYSRST_UART5_CORE>;
> + interrupts = <47>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> +};
> --
> 2.17.1
>
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