linux-kernel - Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow

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Message-ID: <e244c6030c83239f2e33ddd07802d4c32ab182d4.camel@mediatek.com>
Date:   Tue, 4 Oct 2022 09:40:56 +0000
From:   CK Hu (胡俊光) <ck.hu@...iatek.com>
To:     Yongqiang Niu (牛永强) 
        <yongqiang.niu@...iatek.com>,
        "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>
CC:     "jassisinghbrar@...il.com" <jassisinghbrar@...il.com>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "hsinyi@...omium.org" <hsinyi@...omium.org>
Subject: Re: [PATCH v8, 3/4] mailbox: mtk-cmdq: add gce ddr enable support
 flow

Hi, Yongqiang:

On Tue, 2022-10-04 at 17:30 +0800, yongqiang.niu wrote:
> On Mon, 2022-10-03 at 13:04 +0800, CK Hu (胡俊光) wrote:
> > Hi, Yongqiang:
> > 
> > On Sat, 2022-10-01 at 00:06 +0800, Yongqiang Niu wrote:
> > > add gce ddr enable control flow when gce suspend/resume
> > > 
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> > > ---
> > >  drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++
> > >  1 file changed, 22 insertions(+)
> > > 
> > > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > index 04eb44d89119..2db82ff838ed 100644
> > > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > > @@ -94,6 +94,18 @@ struct gce_plat {
> > >  	u32 gce_num;
> > >  };
> > >  
> > > +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> > > +{
> > > +	WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
> > > +
> > > +	if (enable)
> > > +		writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base +
> > > GCE_GCTL_VALUE);
> > > +	else
> > > +		writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE);
> > > +
> > > +	clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
> > > +}
> > > +
> > >  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> > >  {
> > >  	struct cmdq *cmdq = container_of(chan->mbox, struct cmdq,
> > > mbox);
> > > @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev)
> > >  	if (task_running)
> > >  		dev_warn(dev, "exist running task(s) in suspend\n");
> > >  
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, false);
> > 
> > Why do you disable sw ddr function when suspend? Would the problem
> > happen when you disable sw ddr function. 
> > 
> > Regards,
> > CK
> 
> when all cmdq instruction task has been processed done,
> we need set this gce ddr enable to disable status to tell
> cmdq hardware gce there is none task need process, and the hardware
> can go into idle mode and no access ddr anymore, then the spm can go
> into suspend.
> 
> the original issue is gce still access ddr when cmdq suspend function
> call, but there is no task run.
> so, we need control gce access ddr with this flow.
> when cmdq suspend function, there is no task need process, we can
> disable gce access ddr, to make sure system go into suspend success.
> 

OK, and add these explanation to commit message.

> 
> > 
> > > +
> > >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> > >  
> > >  	return 0;
> > > @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev)
> > >  
> > >  	WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
> > >  	cmdq->suspended = false;
> > > +
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, true);
> > > +
> > >  	return 0;
> > >  }
> > >  
> > > @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device
> > > *pdev)
> > >  {
> > >  	struct cmdq *cmdq = platform_get_drvdata(pdev);
> > >  
> > > +	if (cmdq->sw_ddr_en)
> > > +		cmdq_sw_ddr_enable(cmdq, false);
> > > +
> > >  	clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
> > >  	return 0;
> > >  }
> 
>