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Message-ID: <20221006153946.7816-1-ravi.bangoria@amd.com>
Date: Thu, 6 Oct 2022 21:09:38 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: <acme@...nel.org>, <peterz@...radead.org>
CC: <ravi.bangoria@....com>, <jolsa@...nel.org>, <namhyung@...nel.org>,
<eranian@...gle.com>, <irogers@...gle.com>, <jmario@...hat.com>,
<leo.yan@...aro.org>, <alisaidi@...zon.com>, <ak@...ux.intel.com>,
<kan.liang@...ux.intel.com>, <dave.hansen@...ux.intel.com>,
<hpa@...or.com>, <mingo@...hat.com>, <mark.rutland@....com>,
<alexander.shishkin@...ux.intel.com>, <tglx@...utronix.de>,
<bp@...en8.de>, <x86@...nel.org>,
<linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<sandipan.das@....com>, <ananth.narayan@....com>,
<kim.phillips@....com>, <santosh.shukla@....com>
Subject: [PATCH v4 0/8] perf mem/c2c: Add support for AMD (tools changes)
Kernel side of changes are already present in tip/perf/core except
one patch to rename PERF_MEM_LVLNUM_EXTN_MEM to PERF_MEM_LVLNUM_CXL[1].
Original description:
Perf mem and c2c tools are wrappers around perf record with mem load/
store events. IBS tagged load/store sample provides most of the
information needed for these tools. Enable support for these tools on
AMD Zen processors based on IBS Op pmu.
There are some limitations though: Only load/store micro-ops provide
mem/c2c information. Whereas, IBS does not have a way to choose a
particular type of micro-op to tag. This results in many non-LS
micro-ops being tagged which appear as N/A in the perf report. IBS,
being an uncore pmu from kernel point of view[2], does not support per
process monitoring. Thus, perf mem/c2c on AMD are currently supported
in per-cpu mode only.
Example:
$ sudo ./perf mem record -- -c 10000
^C[ perf record: Woken up 227 times to write data ]
[ perf record: Captured and wrote 58.760 MB perf.data (836978 samples) ]
$ sudo ./perf mem report -F mem,sample,snoop
Samples: 836K of event 'ibs_op//', Event count (approx.): 8418762
Memory access Samples Snoop
N/A 700620 N/A
L1 hit 126675 N/A
L2 hit 424 N/A
L3 hit 664 HitM
L3 hit 10 N/A
Local RAM hit 2 N/A
Remote RAM (1 hop) hit 8558 N/A
Remote Cache (1 hop) hit 3 N/A
Remote Cache (1 hop) hit 2 HitM
Remote Cache (2 hops) hit 10 HitM
Remote Cache (2 hops) hit 6 N/A
Uncached hit 4 N/A
Prepared on top of acme/perf/core (3b1913adb188)
v3: https://lore.kernel.org/lkml/20220928095805.596-1-ravi.bangoria@amd.com
v3->v4:
- Rename PERF_MEM_LVLNUM_EXTN_MEM to PERF_MEM_LVLNUM_CXL for tools part.
[1]: https://lore.kernel.org/lkml/f6268268-b4e9-9ed6-0453-65792644d953@amd.com
[2]: https://lore.kernel.org/lkml/20220829113347.295-1-ravi.bangoria@amd.com
Ravi Bangoria (8):
perf tool: Sync include/uapi/linux/perf_event.h header
perf tool: Sync arch/x86/include/asm/amd-ibs.h header
perf mem: Add support for printing PERF_MEM_LVLNUM_{CXL|IO}
perf mem/c2c: Set PERF_SAMPLE_WEIGHT for LOAD_STORE events
perf mem/c2c: Add load store event mappings for AMD
perf mem/c2c: Avoid printing empty lines for unsupported events
perf mem: Print "LFB/MAB" for PERF_MEM_LVLNUM_LFB
perf script: Add missing fields in usage hint
tools/arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++
tools/include/uapi/linux/perf_event.h | 4 ++-
tools/perf/Documentation/perf-c2c.txt | 14 ++++++++---
tools/perf/Documentation/perf-mem.txt | 3 ++-
tools/perf/Documentation/perf-record.txt | 1 +
tools/perf/arch/x86/util/mem-events.c | 31 ++++++++++++++++++++++--
tools/perf/builtin-c2c.c | 1 +
tools/perf/builtin-mem.c | 1 +
tools/perf/builtin-script.c | 7 +++---
tools/perf/util/mem-events.c | 17 +++++++------
10 files changed, 77 insertions(+), 18 deletions(-)
--
2.37.3
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