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Message-ID: <202210080559.hIG2z85r-lkp@intel.com>
Date: Sat, 8 Oct 2022 05:21:25 +0800
From: kernel test robot <lkp@...el.com>
To: Mark Rutland <mark.rutland@....com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [mark:arm64/insn/rework-redo 38/44] arch/arm64/net/bpf_jit.h:243:9:
error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git arm64/insn/rework-redo
head: 425e2601076ee2ff558b953a3abd8fd075bf5e68
commit: 7791b85777814fb76acd694a38e3a1496d65351d [38/44] WIP: arm64: insn: rework logical (shifted register)
config: arm64-allyesconfig
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git/commit/?id=7791b85777814fb76acd694a38e3a1496d65351d
git remote add mark https://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
git fetch --no-tags mark arm64/insn/rework-redo
git checkout 7791b85777814fb76acd694a38e3a1496d65351d
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@...el.com>
Note: the mark/arm64/insn/rework-redo HEAD 425e2601076ee2ff558b953a3abd8fd075bf5e68 builds fine.
It only hurts bisectability.
All error/warnings (new ones prefixed by >>):
In file included from arch/arm64/net/bpf_jit_comp.c:25:
arch/arm64/net/bpf_jit_comp.c: In function 'emit_lse_atomic':
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:254:9: note: in expansion of macro 'A64_LOGIC_SREG'
254 | A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:465:22: note: in expansion of macro 'A64_MVN'
465 | emit(A64_MVN(isdw, tmp2, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:465:22: note: in expansion of macro 'A64_MVN'
465 | emit(A64_MVN(isdw, tmp2, src), ctx);
| ^~~~~~~
In file included from arch/arm64/include/asm/debug-monitors.h:12,
from arch/arm64/include/asm/uprobes.h:9,
from include/linux/uprobes.h:49,
from include/linux/mm_types.h:15,
from include/linux/bpf.h:16,
from arch/arm64/net/bpf_jit_comp.c:11:
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:254:9: note: in expansion of macro 'A64_LOGIC_SREG'
254 | A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:479:22: note: in expansion of macro 'A64_MVN'
479 | emit(A64_MVN(isdw, tmp2, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:479:22: note: in expansion of macro 'A64_MVN'
479 | emit(A64_MVN(isdw, tmp2, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c: In function 'emit_ll_sc_atomic':
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:246:34: note: in expansion of macro 'A64_LOGIC_SREG'
246 | #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:540:30: note: in expansion of macro 'A64_AND'
540 | emit(A64_AND(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:540:30: note: in expansion of macro 'A64_AND'
540 | emit(A64_AND(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:247:34: note: in expansion of macro 'A64_LOGIC_SREG'
247 | #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:542:30: note: in expansion of macro 'A64_ORR'
542 | emit(A64_ORR(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:542:30: note: in expansion of macro 'A64_ORR'
542 | emit(A64_ORR(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:248:34: note: in expansion of macro 'A64_LOGIC_SREG'
248 | #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:544:30: note: in expansion of macro 'A64_EOR'
544 | emit(A64_EOR(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:544:30: note: in expansion of macro 'A64_EOR'
544 | emit(A64_EOR(isdw, tmp2, tmp2, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:246:34: note: in expansion of macro 'A64_LOGIC_SREG'
246 | #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:561:30: note: in expansion of macro 'A64_AND'
561 | emit(A64_AND(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:561:30: note: in expansion of macro 'A64_AND'
561 | emit(A64_AND(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:247:34: note: in expansion of macro 'A64_LOGIC_SREG'
247 | #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:563:30: note: in expansion of macro 'A64_ORR'
563 | emit(A64_ORR(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:563:30: note: in expansion of macro 'A64_ORR'
563 | emit(A64_ORR(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:248:34: note: in expansion of macro 'A64_LOGIC_SREG'
248 | #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:565:30: note: in expansion of macro 'A64_EOR'
565 | emit(A64_EOR(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:565:30: note: in expansion of macro 'A64_EOR'
565 | emit(A64_EOR(isdw, tmp2, src, ax), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:248:34: note: in expansion of macro 'A64_LOGIC_SREG'
248 | #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:586:22: note: in expansion of macro 'A64_EOR'
586 | emit(A64_EOR(isdw, tmp3, r0, tmp2), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:586:22: note: in expansion of macro 'A64_EOR'
586 | emit(A64_EOR(isdw, tmp3, r0, tmp2), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c: In function 'build_insn':
>> arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:246:34: note: in expansion of macro 'A64_LOGIC_SREG'
246 | #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:794:22: note: in expansion of macro 'A64_AND'
794 | emit(A64_AND(is64, dst, dst, src), ctx);
| ^~~~~~~
>> arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:794:22: note: in expansion of macro 'A64_AND'
794 | emit(A64_AND(is64, dst, dst, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:247:34: note: in expansion of macro 'A64_LOGIC_SREG'
247 | #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:798:22: note: in expansion of macro 'A64_ORR'
798 | emit(A64_ORR(is64, dst, dst, src), ctx);
| ^~~~~~~
arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:798:22: note: in expansion of macro 'A64_ORR'
798 | emit(A64_ORR(is64, dst, dst, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:248:34: note: in expansion of macro 'A64_LOGIC_SREG'
248 | #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:802:22: note: in expansion of macro 'A64_EOR'
802 | emit(A64_EOR(is64, dst, dst, src), ctx);
| ^~~~~~~
arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:802:22: note: in expansion of macro 'A64_EOR'
802 | emit(A64_EOR(is64, dst, dst, src), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:246:34: note: in expansion of macro 'A64_LOGIC_SREG'
246 | #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:909:30: note: in expansion of macro 'A64_AND'
909 | emit(A64_AND(is64, dst, dst, tmp), ctx);
| ^~~~~~~
arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:909:30: note: in expansion of macro 'A64_AND'
909 | emit(A64_AND(is64, dst, dst, tmp), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:247:34: note: in expansion of macro 'A64_LOGIC_SREG'
247 | #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
| ^~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:919:30: note: in expansion of macro 'A64_ORR'
919 | emit(A64_ORR(is64, dst, dst, tmp), ctx);
| ^~~~~~~
arch/arm64/net/bpf_jit.h:243:9: error: too few arguments to function 'aarch64_insn_gen_logical_shifted_reg'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:243:9: note: in definition of macro 'A64_LOGIC_SREG'
243 | aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit_comp.c:919:30: note: in expansion of macro 'A64_ORR'
919 | emit(A64_ORR(is64, dst, dst, tmp), ctx);
| ^~~~~~~
arch/arm64/include/asm/insn.h:842:5: note: declared here
842 | u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:244:34: warning: implicit conversion from 'enum aarch64_insn_logic_type' to 'enum aarch64_insn_variant' [-Wenum-conversion]
244 | A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
| ^~~~~~~~~~~~~~~~~~~
arch/arm64/net/bpf_jit.h:248:34: note: in expansion of macro 'A64_LOGIC_SREG'
248 | #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
vim +/aarch64_insn_gen_logical_shifted_reg +243 arch/arm64/net/bpf_jit.h
e54bcde3d69d40 Zi Shen Lim 2014-08-26 240
e54bcde3d69d40 Zi Shen Lim 2014-08-26 241 /* Logical (shifted register) */
e54bcde3d69d40 Zi Shen Lim 2014-08-26 242 #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
e54bcde3d69d40 Zi Shen Lim 2014-08-26 @243 aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
e54bcde3d69d40 Zi Shen Lim 2014-08-26 @244 A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 245 /* Rd = Rn OP Rm */
e54bcde3d69d40 Zi Shen Lim 2014-08-26 246 #define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 247 #define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 248 #define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 249 #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 250 /* Rn & Rm; set condition flags */
e54bcde3d69d40 Zi Shen Lim 2014-08-26 251 #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
1902472b4fa97d Hou Tao 2022-02-17 252 /* Rd = ~Rm (alias of ORN with A64_ZR as Rn) */
1902472b4fa97d Hou Tao 2022-02-17 253 #define A64_MVN(sf, Rd, Rm) \
1902472b4fa97d Hou Tao 2022-02-17 254 A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)
e54bcde3d69d40 Zi Shen Lim 2014-08-26 255
:::::: The code at line 243 was first introduced by commit
:::::: e54bcde3d69d40023ae77727213d14f920eb264a arm64: eBPF JIT compiler
:::::: TO: Zi Shen Lim <zlim.lnx@...il.com>
:::::: CC: Will Deacon <will.deacon@....com>
--
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