linux-kernel - Re: [PATCH v1 2/5] dt-bindings: soc: hpe: Add hpe,gxp-plreg

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 11 Oct 2022 15:27:06 -0500
From:   Rob Herring <robh+dt@...nel.org>
To:     nick.hawkins@....com
Cc:     verdun@....com, krzysztof.kozlowski+dt@...aro.org,
        linux@...linux.org.uk, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 2/5] dt-bindings: soc: hpe: Add hpe,gxp-plreg

On Tue, Oct 11, 2022 at 1:56 PM <nick.hawkins@....com> wrote:
>
> From: Nick Hawkins <nick.hawkins@....com>
>
> The hpe,gxp-plreg binding provides access to the board i/o through the
> Programmable logic interface. The binding provides information to enable
> use of the same driver across the HPE portfolio.
>
> Signed-off-by: Nick Hawkins <nick.hawkins@....com>
> ---
>  .../bindings/soc/hpe/hpe,gxp-plreg.yaml       | 43 +++++++++++++++++++
>  1 file changed, 43 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/hpe/hpe,gxp-plreg.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/hpe/hpe,gxp-plreg.yaml b/Documentation/devicetree/bindings/soc/hpe/hpe,gxp-plreg.yaml
> new file mode 100644
> index 000000000000..cdc54e66d9a9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/hpe/hpe,gxp-plreg.yaml
> @@ -0,0 +1,43 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/hpe/hpe,gxp-plreg.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: HPE GXP Programmable Logic Registers Controller
> +
> +maintainers:
> +  - Nick Hawkins <nick.hawkins@....com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: hpe,gxp-plreg
> +      - const: simple-mfd
> +      - const: syscon
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +
> +additionalProperties: true
> +
> +examples:
> +  - |
> +    cpld@...89000 {
> +      compatible = "hpe,gxp-plreg", "simple-mfd", "syscon";
> +      reg = <0x1e789000 0x1000>;
> +      fan1 {
> +        bit = <0x01>;
> +        inst = <0x27>;
> +        id = <0x2B>;

These property names are way too generic for device specific
properties. There is zero description of what the h/w does and any of
these child nodes to give any advice on direction. However, a node per
register or register field is generally the wrong direction.

Rob