linux-kernel - RE: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent

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Message-ID: <MN2PR12MB4358A871519748CD7A6DB7A089229@MN2PR12MB4358.namprd12.prod.outlook.com>
Date:   Wed, 12 Oct 2022 13:37:54 +0000
From:   "Radovanovic, Aleksandar" <aleksandar.radovanovic@....com>
To:     Jason Gunthorpe <jgg@...pe.ca>
CC:     "Gupta, Nipun" <Nipun.Gupta@....com>,
        Marc Zyngier <maz@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
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Subject: RE: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its
 domain as parent

[AMD Official Use Only - General]



> -----Original Message-----
> From: Jason Gunthorpe <jgg@...pe.ca>
> Sent: 12 October 2022 14:02
> To: Radovanovic, Aleksandar <aleksandar.radovanovic@....com>
> Cc: Gupta, Nipun <Nipun.Gupta@....com>; Marc Zyngier
> <maz@...nel.org>; Robin Murphy <robin.murphy@....com>;
> robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> gregkh@...uxfoundation.org; rafael@...nel.org; eric.auger@...hat.com;
> alex.williamson@...hat.com; cohuck@...hat.com; Gupta, Puneet (DCG-
> ENG) <puneet.gupta@....com>; song.bao.hua@...ilicon.com;
> mchehab+huawei@...nel.org; f.fainelli@...il.com;
> jeffrey.l.hugo@...il.com; saravanak@...gle.com;
> Michael.Srba@...nam.cz; mani@...nel.org; yishaih@...dia.com;
> will@...nel.org; joro@...tes.org; masahiroy@...nel.org;
> ndesaulniers@...gle.com; linux-arm-kernel@...ts.infradead.org; linux-
> kbuild@...r.kernel.org; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org; kvm@...r.kernel.org; okaya@...nel.org;
> Anand, Harpreet <harpreet.anand@....com>; Agarwal, Nikhil
> <nikhil.agarwal@....com>; Simek, Michal <michal.simek@....com>; git
> (AMD-Xilinx) <git@....com>
> Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its
> domain as parent
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Wed, Oct 12, 2022 at 10:34:23AM +0000, Radovanovic, Aleksandar wrote:
> 
> 
> > As for GITS_TRANSLATER, we can take up to 4 different IOVAs, which
> > limits us to 4 CDX devices (should be sufficient for current HW
> > use-cases). Also, it means that the address part must be the same for
> > all vectors within a single CDX device. I'm assuming this is OK as it
> > is going to be a single interrupt and IOMMU domain anyway.
> 
> This is not at all how MSI is supposed to work.

In the general case, no, they're not. However, this is an embedded device
with a GICv3, so the general case does not really apply. On GIC, the MSI 
target address is always a fixed register in the ITS (GIC_TRANSLATER), 
possibly SMMU translated. As long as the translation is consistent across
a single device (and I see no reason why or how the kernel would do it 
otherwise, given that a single CDX device generates the same StreamID
for all MSI writes), the GIC IOVA should be the same for all vectors of 
the device.

It is worth noting that this limitation is not going to be baked in the 
proposed MSI configuration interface, it will still take both the address
and data parts for each vector. It is just that this particular 
implementation will throw an error if you supply a different target
address across device MSI vectors. It does not preclude some future
device accepting different addresses per vector over the same 
interface.

Thanks,
Aleksandar