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Message-ID: <Y0n0o0r85ldlLMqp@iweiny-desk3>
Date: Fri, 14 Oct 2022 16:45:39 -0700
From: Ira Weiny <ira.weiny@...el.com>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
CC: Dan Williams <dan.j.williams@...el.com>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
"Ben Widawsky" <bwidawsk@...nel.org>,
Steven Rostedt <rostedt@...dmis.org>,
Davidlohr Bueso <dave@...olabs.net>,
<linux-kernel@...r.kernel.org>, <linux-cxl@...r.kernel.org>
Subject: Re: [RFC V2 PATCH 06/11] cxl/mem: Trace DRAM Event Record
On Tue, Oct 11, 2022 at 02:47:12PM +0100, Jonathan Cameron wrote:
> On Mon, 10 Oct 2022 15:41:26 -0700
> ira.weiny@...el.com wrote:
>
> > From: Ira Weiny <ira.weiny@...el.com>
> >
> > CXL rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record.
> >
> > Determine if the event read is a DRAM event record and if so trace the
> > record.
> >
> > Signed-off-by: Ira Weiny <ira.weiny@...el.com>
> >
>
> Trivial comments inline
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
>
> > diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
> > index 82a8d3b750a2..7a90cfea348b 100644
> > --- a/include/trace/events/cxl.h
> > +++ b/include/trace/events/cxl.h
> > @@ -230,6 +230,100 @@ TRACE_EVENT(general_media,
> > )
> > );
> >
>
> > +
> > +TRACE_EVENT(dram,
> > +
> > + TP_PROTO(const char *dev_name, enum cxl_event_log_type log,
> > + struct cxl_event_dram *rec),
> > +
> > + TP_ARGS(dev_name, log, rec),
> > +
> > + TP_STRUCT__entry(
> > + CXL_EVT_TP_entry
> > + /* DRAM */
> > + __field(u64, phys_addr)
> > + __field(u8, descriptor)
> > + __field(u8, type)
> > + __field(u8, transaction_type)
> > + __field(u8, channel)
> > + __field(u16, validity_flags)
> > + __field(u16, column) /* Out of order to pack trace record */
> > + __field(u32, nibble_mask)
> > + __field(u32, row)
> > + __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE)
> > + __array(u8, reserved, CXL_EVENT_DER_RES_SIZE)
>
> If we are going to have this, why not put it at the end? Will that affect the
> packing badly?
I removed it.
[snip]
> > +
> > + CXL_EVT_TP_printk("phys_addr=%llx volatile=%s desc='%s' type='%s' " \
> > + "trans_type='%s' channel=%u rank=%u nibble_mask=%x " \
> > + "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \
> > + "valid_flags='%s' reserved=%s",
> > + __entry->phys_addr & CXL_GMER_PHYS_ADDR_MASK,
> > + (__entry->phys_addr & CXL_GMER_PHYS_ADDR_VOLATILE) ? "TRUE" : "FALSE",
> > + show_event_desc_flags(__entry->descriptor),
> > + show_mem_event_type(__entry->type),
> > + show_trans_type(__entry->transaction_type),
> > + __entry->channel, __entry->rank, __entry->nibble_mask,
> > + __entry->bank_group, __entry->bank,
> > + __entry->row, __entry->column,
> > + __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE),
> > + show_dram_valid_flags(__entry->validity_flags),
> > + __print_hex(__entry->reserved, CXL_EVENT_DER_RES_SIZE)
> > + )
> Probably one less tab on that trailing )?
Done.
Thanks!
Ira
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