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Date: Tue, 18 Oct 2022 15:31:16 +0200
From: "Rafael J. Wysocki" <rafael@...nel.org>
To: Robert Richter <rrichter@....com>
Cc: Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
Dan Williams <dan.j.williams@...el.com>,
linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
Bjorn Helgaas <bhelgaas@...gle.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Davidlohr Bueso <dave@...olabs.net>,
Terry Bowman <terry.bowman@....com>
Subject: Re: [PATCH v2 06/12] cxl/acpi: Extract component registers of
restricted hosts from RCRB
On Tue, Oct 18, 2022 at 3:24 PM Robert Richter <rrichter@....com> wrote:
>
> A downstream port must be connected to a component register block.
> For restricted hosts the base address is determined from the RCRB. The
> RCRB is provided by the host's CEDT CHBS entry. Rework CEDT parser to
> get the RCRB and add code to extract the component register block from
> it.
>
> RCRB's BAR[0..1] point to the component block containing CXL subsystem
> component registers. MEMBAR extraction follows the PCI base spec here,
> esp. 64 bit extraction and memory range alignment (6.0, 7.5.1.2.1).
>
> Note: Right now the component register block is used for HDM decoder
> capability only which is optional for RCDs. If unsupported by the RCD,
> the HDM init will fail. It is future work to bypass it in this case.
>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
What does this S-o-B mean? If this person is your co-developer, you
need to add a Co-developed-by tag to clarify that.
> Signed-off-by: Robert Richter <rrichter@....com>
> ---
> drivers/cxl/acpi.c | 79 ++++++++++++++++++++++++++++++++++++++++------
> 1 file changed, 69 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index fb9f72813067..a92d5d7b7a92 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -9,6 +9,8 @@
> #include "cxlpci.h"
> #include "cxl.h"
>
> +#define CXL_RCRB_SIZE SZ_8K
> +
> static unsigned long cfmws_to_decoder_flags(int restrictions)
> {
> unsigned long flags = CXL_DECODER_F_ENABLE;
> @@ -229,27 +231,82 @@ static int add_host_bridge_uport(struct device *match, void *arg)
> struct cxl_chbs_context {
> struct device *dev;
> unsigned long long uid;
> - resource_size_t chbcr;
> + struct acpi_cedt_chbs chbs;
> };
>
> -static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
> - const unsigned long end)
> +static int cxl_get_chbs(union acpi_subtable_headers *header, void *arg,
> + const unsigned long end)
> {
> struct cxl_chbs_context *ctx = arg;
> struct acpi_cedt_chbs *chbs;
>
> - if (ctx->chbcr)
> + if (ctx->chbs.base)
> return 0;
>
> chbs = (struct acpi_cedt_chbs *) header;
>
> if (ctx->uid != chbs->uid)
> return 0;
> - ctx->chbcr = chbs->base;
> + ctx->chbs = *chbs;
>
> return 0;
> }
>
> +static resource_size_t cxl_get_chbcr(struct cxl_chbs_context *ctx)
> +{
> + struct acpi_cedt_chbs *chbs = &ctx->chbs;
> + resource_size_t component_reg_phys, rcrb;
> + u32 bar0, bar1;
> + void *addr;
> +
> + if (!chbs->base)
> + return CXL_RESOURCE_NONE;
> +
> + if (chbs->cxl_version != ACPI_CEDT_CHBS_VERSION_CXL11)
> + return chbs->base;
> +
> + /* Extract RCRB */
> +
> + if (chbs->length != CXL_RCRB_SIZE)
> + return CXL_RESOURCE_NONE;
> +
> + rcrb = chbs->base;
> +
> + dev_dbg(ctx->dev, "RCRB found for UID %lld: 0x%08llx\n",
> + ctx->uid, (u64)rcrb);
> +
> + /*
> + * RCRB's BAR[0..1] point to component block containing CXL
> + * subsystem component registers. MEMBAR extraction follows
> + * the PCI Base spec here, esp. 64 bit extraction and memory
> + * ranges alignment (6.0, 7.5.1.2.1).
> + */
> + addr = ioremap(rcrb, PCI_BASE_ADDRESS_0 + SZ_8);
> + bar0 = readl(addr + PCI_BASE_ADDRESS_0);
> + bar1 = readl(addr + PCI_BASE_ADDRESS_1);
> + iounmap(addr);
> +
> + /* sanity check */
> + if (bar0 & (PCI_BASE_ADDRESS_MEM_TYPE_1M | PCI_BASE_ADDRESS_SPACE_IO))
> + return CXL_RESOURCE_NONE;
> +
> + component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK;
> + if (bar0 & PCI_BASE_ADDRESS_MEM_TYPE_64)
> + component_reg_phys |= ((u64)bar1) << 32;
> +
> + if (!component_reg_phys)
> + return CXL_RESOURCE_NONE;
> +
> + /*
> + * Must be 8k aligned (size of combined CXL 1.1 Downstream and
> + * Upstream Port RCRBs).
> + */
> + if (component_reg_phys & (CXL_RCRB_SIZE - 1))
> + return CXL_RESOURCE_NONE;
> +
> + return component_reg_phys;
> +}
> +
> static int add_host_bridge_dport(struct device *match, void *arg)
> {
> acpi_status status;
> @@ -259,6 +316,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
> struct cxl_port *root_port = arg;
> struct device *host = root_port->dev.parent;
> struct acpi_device *bridge = to_cxl_host_bridge(host, match);
> + resource_size_t component_reg_phys;
>
> if (!bridge)
> return 0;
> @@ -273,19 +331,20 @@ static int add_host_bridge_dport(struct device *match, void *arg)
> dev_dbg(match, "UID found: %lld\n", uid);
>
> ctx = (struct cxl_chbs_context) {
> - .dev = host,
> + .dev = match,
> .uid = uid,
> };
> - acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
> + acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbs, &ctx);
>
> - if (ctx.chbcr == 0) {
> + component_reg_phys = cxl_get_chbcr(&ctx);
> + if (component_reg_phys == CXL_RESOURCE_NONE) {
> dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n", uid);
> return 0;
> }
>
> - dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)ctx.chbcr);
> + dev_dbg(match, "CHBCR found: 0x%08llx\n", (u64)component_reg_phys);
>
> - dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
> + dport = devm_cxl_add_dport(root_port, match, uid, component_reg_phys);
> if (IS_ERR(dport))
> return PTR_ERR(dport);
>
> --
> 2.30.2
>
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