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Message-Id: <20221021084708.1109986-2-bchihi@baylibre.com>
Date: Fri, 21 Oct 2022 10:47:07 +0200
From: bchihi@...libre.com
To: sean.wang@...nel.org, linus.walleij@...aro.org,
matthias.bgg@...il.com
Cc: linux-mediatek@...ts.infradead.org, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: [v2, 1/2] pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes
From: Balsam CHIHI <bchihi@...libre.com>
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Add mt8365_set_clr_mode() callback for such SoCs, so that instead of
using the SET/CLR register, use the main R/W register to
read/update/write the modes.
Co-developed-by: Fabien Parent <fparent@...libre.com>
Signed-off-by: Fabien Parent <fparent@...libre.com>
Signed-off-by: Balsam CHIHI <bchihi@...libre.com>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index f25b3e09386b..076ae0b38e3d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
return -EINVAL;
}
+ if (pctl->devdata->mt8365_set_clr_mode) {
+ bit = pin & pctl->devdata->mode_mask;
+ reg_pullen = mtk_get_port(pctl, pin) +
+ pctl->devdata->pullen_offset;
+ reg_pullsel = mtk_get_port(pctl, pin) +
+ pctl->devdata->pullsel_offset;
+ ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
+ bit, reg_pullen, reg_pullsel,
+ enable, isup);
+ if (ret)
+ return -EINVAL;
+
+ return 0;
+ }
+
bit = BIT(pin & pctl->devdata->mode_mask);
if (enable)
reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 6fe8564334c9..11afa12a96cb 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -216,7 +216,10 @@ struct mtk_eint_offsets {
* @spec_dir_set: In very few SoCs, direction control registers are not
* arranged continuously, they may be cut to parts. So they need special
* dir setting.
-
+ * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they
+ * need to use the main R/W register to read/update/write the modes instead of
+ * the SET/CLR register.
+ *
* @dir_offset: The direction register offset.
* @pullen_offset: The pull-up/pull-down enable register offset.
* @pinmux_offset: The pinmux register offset.
@@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata {
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
unsigned int mode);
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
+ int (*mt8365_set_clr_mode)(struct regmap *regmap,
+ unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
+ bool enable, bool isup);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;
--
2.34.1
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