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Message-ID: <CAJF2gTRdtcpccL5W48O8VEXCMvxNAyyrKJzhwNJkc8js+H2iJg@mail.gmail.com>
Date: Fri, 21 Oct 2022 22:41:33 +0800
From: Guo Ren <guoren@...nel.org>
To: Tong Tiangen <tongtiangen@...wei.com>
Cc: Andrea Parri <parri.andrea@...il.com>,
Jisheng Zhang <jszhang@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: fix race when vmap stack overflow
On Fri, Oct 21, 2022 at 9:46 PM Tong Tiangen <tongtiangen@...wei.com> wrote:
>
>
>
> 在 2022/10/21 21:22, Andrea Parri 写道:
> > Hi Tong,
> >
> >>>> I use atomic_set_release here, because I need earlier memory
> >>>> operations finished to make sure the sp is ready then set the spin
> >>>> flag.
> >
> >> Consider this implementation:)
> >>
> >> smp_store_mb(&spin_shadow_stack, 0);
> >
> > smp_store_mb() has "WRITE_ONCE(); smp_mb()" semantics; so it doesn't
> > guarantee that the store to spin_shadow_stack is ordered after program
> > -order earlier memory accesses.
> >
> > Andrea
> > .
>
> Hi Andrea:
>
> IIUC, the earlier memory access amoswap.aqrl, here .aqrl guarantee it.
> But anyway, consider we don't care about performance here, using
> smp_store_release()(add barrier()) surely right.
We use smp_store_release() is for:
//load per-cpu overflow stack
REG_L sp, -8(sp)
Not amoswap.
Actually, amoswap.aqrl guarantees nothing because all instructions
depend on the sp register.
>
> Thanks,
> Tong.
--
Best Regards
Guo Ren
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