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Message-ID: <41608bda-3c20-060e-a9b4-afa2fe615b41@huawei.com>
Date:   Fri, 21 Oct 2022 23:17:52 +0800
From:   Tong Tiangen <tongtiangen@...wei.com>
To:     Guo Ren <guoren@...nel.org>
CC:     Andrea Parri <parri.andrea@...il.com>,
        Jisheng Zhang <jszhang@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        <linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] riscv: fix race when vmap stack overflow



在 2022/10/21 22:41, Guo Ren 写道:
> On Fri, Oct 21, 2022 at 9:46 PM Tong Tiangen <tongtiangen@...wei.com> wrote:
>>
>>
>>
>> 在 2022/10/21 21:22, Andrea Parri 写道:
>>> Hi Tong,
>>>
>>>>>> I use atomic_set_release here, because I need earlier memory
>>>>>> operations finished to make sure the sp is ready then set the spin
>>>>>> flag.
>>>
>>>>       Consider this implementation:)
>>>>
>>>>       smp_store_mb(&spin_shadow_stack, 0);
>>>
>>> smp_store_mb() has "WRITE_ONCE(); smp_mb()" semantics; so it doesn't
>>> guarantee that the store to spin_shadow_stack is ordered after program
>>> -order earlier memory accesses.
>>>
>>>     Andrea
>>> .
>>
>> Hi Andrea:
>>
>> IIUC, the earlier memory access amoswap.aqrl, here .aqrl guarantee it.
>> But anyway, consider we don't care about performance here, using
>> smp_store_release()(add barrier()) surely right.
> We use smp_store_release() is for:
>          //load per-cpu overflow stack
>          REG_L sp, -8(sp)

Oh, missing that, you're right. This guarantee the spin flag is set 
after the sp is used.

> 
> Not amoswap.
> 
> Actually, amoswap.aqrl guarantees nothing because all instructions
> depend on the sp register.
right.

Thanks,
Tong.

> 
>>
>> Thanks,
>> Tong.
> 
> 
> 

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