linux-kernel - [PATCH 1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache

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Message-Id: <20221023133205.3493564-2-guoren@kernel.org>
Date:   Sun, 23 Oct 2022 09:32:04 -0400
From:   guoren@...nel.org
To:     guoren@...nel.org, palmer@...belt.com, palmer@...osinc.com,
        heiko@...ech.de, arnd@...db.de, songmuchun@...edance.com,
        catalin.marinas@....com, chenhuacai@...ngson.cn,
        Conor.Dooley@...rochip.com, paul.walmsley@...ive.com,
        aou@...s.berkeley.edu
Cc:     linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-mm@...ck.org,
        Guo Ren <guoren@...ux.alibaba.com>,
        Will Deacon <will@...nel.org>,
        Steven Price <steven.price@....com>
Subject: [PATCH 1/2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte

From: Guo Ren <guoren@...ux.alibaba.com>

RISC-V follows the arm64 flush_icache_pte mechanism and also includes
its bug. The patch ensures that instructions are observable in a new
mapping. For more details, see 588a513d3425 ("arm64: Fix race condition
on PG_dcache_clean in __sync_icache_dcache()").

Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Guo Ren <guoren@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Will Deacon <will@...nel.org>
Cc: Steven Price <steven.price@....com>
---
 arch/riscv/mm/cacheflush.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 6cb7d96ad9c7..7c9f97fa3938 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -82,7 +82,9 @@ void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
-	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
 }
 #endif /* CONFIG_MMU */
-- 
2.36.1