linux-kernel - [PATCH v2] x86/cpu: replacing the open-coded shift with BIT(x)

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Message-ID: <20221101111418.816139-1-cuigaosheng1@huawei.com>
Date:   Tue, 1 Nov 2022 19:14:18 +0800
From:   Gaosheng Cui <cuigaosheng1@...wei.com>
To:     <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
        <dave.hansen@...ux.intel.com>, <x86@...nel.org>, <hpa@...or.com>,
        <puwen@...on.cn>, <TonyWWang-oc@...oxin.com>, <Jason@...c4.com>,
        <peterz@...radead.org>, <gregkh@...uxfoundation.org>,
        <cuigaosheng1@...wei.com>, <andrew.cooper3@...rix.com>,
        <tony.luck@...el.com>, <mario.limonciello@....com>,
        <pawan.kumar.gupta@...ux.intel.com>, <chenyi.qiang@...el.com>,
        <rdunlap@...radead.org>, <jithu.joseph@...el.com>,
        <rafael.j.wysocki@...el.com>, <paulmck@...nel.org>
CC:     <linux-kernel@...r.kernel.org>
Subject: [PATCH v2] x86/cpu: replacing the open-coded shift with BIT(x)

Replace the open-coded shift with BIT(x) to make the code a bit
more self-documenting, at the same time, fix some useless warnings.

Signed-off-by: Gaosheng Cui <cuigaosheng1@...wei.com>
---
v2:
- Change the commit msg, remove the UBSAN warning calltrace, and
  merge patch "x86/cpu: fix undefined behavior in bit shift for
  intel_detect_tlb" with it. Thanks!
 arch/x86/kernel/cpu/amd.c     | 2 +-
 arch/x86/kernel/cpu/centaur.c | 2 +-
 arch/x86/kernel/cpu/hygon.c   | 2 +-
 arch/x86/kernel/cpu/intel.c   | 4 ++--
 arch/x86/kernel/cpu/proc.c    | 2 +-
 arch/x86/kernel/cpu/zhaoxin.c | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 860b60273df3..75d82cad323a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -613,7 +613,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 	 * with P/T states and does not stop in deep C-states
 	 */
-	if (c->x86_power & (1 << 8)) {
+	if (c->x86_power & BIT(8)) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d905db6..9910bb1d90fd 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -105,7 +105,7 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 #endif
-	if (c->x86_power & (1 << 8)) {
+	if (c->x86_power & BIT(8)) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 21fd425088fe..dc473bfbf1b5 100644
--- a/arch/x86/kernel/cpu/hygon.c
x86/cpu: fix undefined behavior in bit shift for intel_detect_tlb+++ b/arch/x86/kernel/cpu/hygon.c
@@ -251,7 +251,7 @@ static void early_init_hygon(struct cpuinfo_x86 *c)
 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 	 * with P/T states and does not stop in deep C-states
 	 */
-	if (c->x86_power & (1 << 8)) {
+	if (c->x86_power & BIT(8)) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 2d7ea5480ec3..2bdf6d601a6f 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -286,7 +286,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 	 * It is also reliable across cores and sockets. (but not across
 	 * cabinets - we turn it off in that case explicitly.)
 	 */
-	if (c->x86_power & (1 << 8)) {
+	if (c->x86_power & BIT(8)) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
@@ -945,7 +945,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 
 		/* If bit 31 is set, this is an unknown format */
 		for (j = 0 ; j < 3 ; j++)
-			if (regs[j] & (1 << 31))
+			if (regs[j] & BIT(31))
 				regs[j] = 0;
 
 		/* Byte 0 is level count, not a descriptor */
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 099b6f0d96bd..efa1d39c4f25 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -135,7 +135,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 
 	seq_puts(m, "power management:");
 	for (i = 0; i < 32; i++) {
-		if (c->x86_power & (1 << i)) {
+		if (c->x86_power & BIT(i)) {
 			if (i < ARRAY_SIZE(x86_power_flags) &&
 			    x86_power_flags[i])
 				seq_printf(m, "%s%s",
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef63490..34a8a460f8f4 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -61,7 +61,7 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 #endif
-	if (c->x86_power & (1 << 8)) {
+	if (c->x86_power & BIT(8)) {
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
-- 
2.25.1