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Date:   Tue, 1 Nov 2022 17:25:36 +0200 (EET)
From:   Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To:     Tharunkumar.Pasumarthi@...rochip.com
cc:     Kumaravel.Thiagarajan@...rochip.com,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jiri Slaby <jirislaby@...nel.org>, andy.shevchenko@...il.com,
        u.kleine-koenig@...gutronix.de, johan@...nel.org,
        wander@...hat.com, etremblay@...tech-controls.com,
        macro@...am.me.uk, geert+renesas@...der.be, jk@...abs.org,
        phil.edworthy@...esas.com, Lukas Wunner <lukas@...ner.de>,
        LKML <linux-kernel@...r.kernel.org>,
        linux-serial <linux-serial@...r.kernel.org>,
        UNGLinuxDriver@...rochip.com
Subject: RE: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
 support to quad-uart driver.

On Tue, 1 Nov 2022, Tharunkumar.Pasumarthi@...rochip.com wrote:

> > From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
> > Sent: Monday, October 3, 2022 2:34 PM
> > To: Kumaravel Thiagarajan - I21417
> > <Kumaravel.Thiagarajan@...rochip.com>
> > Subject: Re: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
> > support to quad-uart driver.
> > 
> > [Some people who received this message don't often get email from
> > ilpo.jarvinen@...ux.intel.com. Learn why this is important at
> > https://aka.ms/LearnAboutSenderIdentification ]
> > 
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
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> > 
> > > +     if (rs485->flags & SER_RS485_ENABLED) {
> > > +             memset(rs485->padding, 0, sizeof(rs485->padding));
> > 
> > Core handles this for you.
> 
> I went through the code and it seems like this is not taken care by the core.
> Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
> This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.
> 
> > > +             if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) {
> > > +                     data |= ADCL_CFG_POL_SEL;
> > > +                     rs485->flags |=  SER_RS485_RTS_AFTER_SEND;
> > > +             } else {
> > > +                     rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
> > > +             }
> > 
> > Core handles that flags sanitization for you.
> 
> I went through the code and it seems like this is not taken care by the core.
> Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
> This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.
> 
> > > +     } else {
> > > +             memset(rs485, 0, sizeof(*rs485));
> > 
> > Core handles this.
> 
> I went through the code and it seems like this is not taken care by the core.
> Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
> This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.
> 
> > > +     writeb(data, (port->membase + ADCL_CFG_REG));
> > > +     port->rs485 = *rs485;
> > 
> > Core handles this.
> 
> I went through the code and it seems like this is not taken care by the core.
> Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
> This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.

It has nothing to do with serial8250_em485_config.

It is very hard to believe you couldn't find 
uart_sanitize_serial_rs485() and uart_set_rs485_config() yourself, the 
latter calls your driver specific rs485 handler.

-- 
 i.

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