lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 2 Nov 2022 19:14:52 +0000
From:   "Elliott, Robert (Servers)" <elliott@....com>
To:     "H. Peter Anvin" <hpa@...or.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Borislav Petkov <bp@...en8.de>,
        Maxim Levitsky <mlevitsk@...hat.com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
        Ingo Molnar <mingo@...hat.com>,
        "Josh Poimboeuf" <jpoimboe@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        "Tony Luck" <tony.luck@...el.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        "David S. Miller" <davem@...emloft.net>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "Chang S. Bae" <chang.seok.bae@...el.com>,
        Jane Malalane <jane.malalane@...rix.com>,
        Kees Cook <keescook@...omium.org>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Peter Zijlstra <peterz@...radead.org>,
        "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
        "Herbert Xu" <herbert@...dor.apana.org.au>,
        Jiri Olsa <jolsa@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "linux-perf-users@...r.kernel.org" <linux-perf-users@...r.kernel.org>,
        "open list:CRYPTO API" <linux-crypto@...r.kernel.org>
Subject: RE: [PATCH v2 1/5] perf/x86/intel/lbr: use setup_clear_cpu_cap
 instead of clear_cpu_cap


> >We have a dependency system for CPUID features. If you are going to do
> this (as opposed to "fixing" this in Qemu or just saying "don't do that,
> it isn't a valid hardware configuration."
> One more thing: for obvious reasons, this doesn't fix user space if user
> space calls CPUID directly as opposed to reading /proc/cpuinfo or looking
> in sysfs. Unfortunately this is the rule rather than the exception,
> although for some features like AVX user space is also supposed to check
> XCR0, in which case it will work properly anyway.

The x86 crypto modules use boot_cpu_has() to check features before
using them.

If that (or some other function that we change them to use) returned false 
if the necessary XSAVE bits were not set, then they could drop the
cpu_has_xfeatures() calls.

arch/x86/kernel/fpu/xstate.c, which provides cpu_has_xfeatures(),
and also has an xsave_cpu_features table listing the features needed
be each xfeature. Perhaps that should provide a cpu_feature_usable()
function that calls boot_cpu_has() and confirms the associated xfeatures
are present. That way the logic would be in one place rather than
replicated in 20+ crypto modules.


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ