[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20221103223956.50575-2-fabrizio.castro.jz@renesas.com>
Date: Thu, 3 Nov 2022 22:39:54 +0000
From: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Magnus Damm <magnus.damm@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-watchdog@...r.kernel.org,
Chris Paterson <Chris.Paterson2@...esas.com>,
Biju Das <biju.das@...renesas.com>,
Fabrizio Castro <fabrizio.castro@...renesas.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Jacopo Mondi <jacopo@...ndi.org>
Subject: [PATCH 1/3] watchdog: rzg2l_wdt: Fix reboot for RZ/V2M
The setting for the RZ/V2M watchdog cannot be changed once
the watchdog has been enabled, unless the IP gets reset.
The current implementation of the restart callback assumes
that the watchdog is not enabled, but that's not always the
case, and it leads to longer than necessary reboot times if
the watchdog is already running.
Always reset the RZ/V2M watchdog first, so that we can always
restart quickly.
Fixes: ec122fd94eeb ("watchdog: rzg2l_wdt: Add rzv2m support")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
---
drivers/watchdog/rzg2l_wdt.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
index 974a4194a8fd..00438ceed17a 100644
--- a/drivers/watchdog/rzg2l_wdt.c
+++ b/drivers/watchdog/rzg2l_wdt.c
@@ -145,10 +145,10 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,
{
struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
- clk_prepare_enable(priv->pclk);
- clk_prepare_enable(priv->osc_clk);
-
if (priv->devtype == WDT_RZG2L) {
+ clk_prepare_enable(priv->pclk);
+ clk_prepare_enable(priv->osc_clk);
+
/* Generate Reset (WDTRSTB) Signal on parity error */
rzg2l_wdt_write(priv, 0, PECR);
@@ -157,6 +157,11 @@ static int rzg2l_wdt_restart(struct watchdog_device *wdev,
} else {
/* RZ/V2M doesn't have parity error registers */
+ reset_control_reset(priv->rstc);
+
+ clk_prepare_enable(priv->pclk);
+ clk_prepare_enable(priv->osc_clk);
+
wdev->timeout = 0;
/* Initialize time out */
--
2.34.1
Powered by blists - more mailing lists