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Message-ID: <e6d97b24-caa6-f945-0379-7eeeb12f1fb2@rivosinc.com>
Date: Thu, 3 Nov 2022 21:10:28 -0700
From: Vineet Gupta <vineetg@...osinc.com>
To: Chris Stillson <stillson@...osinc.com>
Cc: Greentime Hu <greentime.hu@...ive.com>,
Guo Ren <guoren@...ux.alibaba.com>,
Vincent Chen <vincent.chen@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Eric Biederman <ebiederm@...ssion.com>,
Kees Cook <keescook@...omium.org>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Oleg Nesterov <oleg@...hat.com>, Guo Ren <guoren@...nel.org>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Arnaud Pouliquen <arnaud.pouliquen@...s.st.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Alexandre Ghiti <alexandre.ghiti@...onical.com>,
Arnd Bergmann <arnd@...db.de>,
Heiko Stuebner <heiko@...ech.de>,
Jisheng Zhang <jszhang@...nel.org>,
Dao Lu <daolu@...osinc.com>,
Sunil V L <sunilvl@...tanamicro.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
lkml <linux-kernel@...r.kernel.org>, linux-mm@...ck.org
Subject: Re: [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save
vector features.
On 9/21/22 14:43, Chris Stillson wrote:
> From: Greentime Hu <greentime.hu@...ive.com>
>
> This patch is used to detect vector support status of CPU and use
> riscv_vsize to save the size of all the vector registers. It assumes
> all harts has the same capabilities in SMP system.
Patch title is horrible. The meat of patch is vector state save/restore,
but no users of it yet. And then there are random unrelated snippets
thrown in same patch.
>
> [guoren@...ux.alibaba.com: add has_vector checking]
> Co-developed-by: Guo Ren <guoren@...ux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen@...ive.com>
> Signed-off-by: Vincent Chen <vincent.chen@...ive.com>
> Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> ---
> arch/riscv/include/asm/vector.h | 14 +++++
> arch/riscv/kernel/cpufeature.c | 19 +++++++
> arch/riscv/kernel/riscv_ksyms.c | 6 +++
> arch/riscv/kernel/vector.S | 93 +++++++++++++++++++++++++++++++++
> 4 files changed, 132 insertions(+)
> create mode 100644 arch/riscv/include/asm/vector.h
> create mode 100644 arch/riscv/kernel/vector.S
>
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> new file mode 100644
> index 000000000000..16304b0c6a6f
> --- /dev/null
> +++ b/arch/riscv/include/asm/vector.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (C) 2020 SiFive
> + */
> +
> +#ifndef __ASM_RISCV_VECTOR_H
> +#define __ASM_RISCV_VECTOR_H
> +
> +#include <linux/types.h>
> +
> +void rvv_enable(void);
> +void rvv_disable(void);
> +
> +#endif /* ! __ASM_RISCV_VECTOR_H */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8d4448c2d4f4..0487ab19b234 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -30,6 +30,14 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> EXPORT_SYMBOL(riscv_isa_ext_keys);
> +#ifdef CONFIG_FPU
> +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
> +#endif
This needs to be broken out to a FPU patch which actually uses
cpu_hwcap_fpu.
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
> +unsigned long riscv_vsize __read_mostly;
> +#endif
I would have moved all the detection code to patch 2/17 - including the
static branch definition and enable below (except for vlen stuff)
>
> /**
> * riscv_isa_extension_base() - Get base extension word
> @@ -249,6 +257,16 @@ void __init riscv_fill_hwcap(void)
> if (j >= 0)
> static_branch_enable(&riscv_isa_ext_keys[j]);
> }
> +
> +#ifdef CONFIG_VECTOR
> + if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
> + static_branch_enable(&cpu_hwcap_vector);
> + /* There are 32 vector registers with vlenb length. */
> + rvv_enable();
> + riscv_vsize = csr_read(CSR_VLENB) * 32;
> + rvv_disable();
> + }
> +#endif
> }
>
> #ifdef CONFIG_RISCV_ALTERNATIVE
> @@ -328,3 +346,4 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> }
> }
> #endif
> +}
> diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksyms.c
> index 5ab1c7e1a6ed..3489d2a20ca3 100644
> --- a/arch/riscv/kernel/riscv_ksyms.c
> +++ b/arch/riscv/kernel/riscv_ksyms.c
> @@ -15,3 +15,9 @@ EXPORT_SYMBOL(memmove);
> EXPORT_SYMBOL(__memset);
> EXPORT_SYMBOL(__memcpy);
> EXPORT_SYMBOL(__memmove);
> +
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +EXPORT_SYMBOL(rvv_enable);
> +EXPORT_SYMBOL(rvv_disable);
> +#endif
> diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
> new file mode 100644
> index 000000000000..9f7dc70c4443
> --- /dev/null
> +++ b/arch/riscv/kernel/vector.S
> @@ -0,0 +1,93 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2017 SiFive
> + * Copyright (C) 2019 Alibaba Group Holding Limited
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation, version 2.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/linkage.h>
> +
> +#include <asm/asm.h>
> +#include <asm/csr.h>
> +#include <asm/asm-offsets.h>
> +
> +#define vstatep a0
> +#define datap a1
> +#define x_vstart t0
> +#define x_vtype t1
> +#define x_vl t2
> +#define x_vcsr t3
> +#define incr t4
> +#define status t5
> +
A few words here as to when is this save/restore done.
Best to do this in the patch which actually uses this code.
> +ENTRY(__vstate_save)
> + li status, SR_VS
> + csrs CSR_STATUS, status
> +
> + csrr x_vstart, CSR_VSTART
> + csrr x_vtype, CSR_VTYPE
> + csrr x_vl, CSR_VL
> + csrr x_vcsr, CSR_VCSR
> + vsetvli incr, x0, e8, m8, ta, ma
> + vse8.v v0, (datap)
> + add datap, datap, incr
> + vse8.v v8, (datap)
> + add datap, datap, incr
> + vse8.v v16, (datap)
> + add datap, datap, incr
> + vse8.v v24, (datap)
> +
> + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
> + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
> + REG_S x_vl, RISCV_V_STATE_VL(vstatep)
> + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> +
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(__vstate_save)
> +
> +ENTRY(__vstate_restore)
> + li status, SR_VS
> + csrs CSR_STATUS, status
> +
> + vsetvli incr, x0, e8, m8, ta, ma
> + vle8.v v0, (datap)
> + add datap, datap, incr
> + vle8.v v8, (datap)
> + add datap, datap, incr
> + vle8.v v16, (datap)
> + add datap, datap, incr
> + vle8.v v24, (datap)
> +
> + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep)
> + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep)
> + REG_L x_vl, RISCV_V_STATE_VL(vstatep)
> + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> + vsetvl x0, x_vl, x_vtype
> + csrw CSR_VSTART, x_vstart
> + csrw CSR_VCSR, x_vcsr
> +
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(__vstate_restore)
> +
> +ENTRY(rvv_enable)
> + li status, SR_VS
> + csrs CSR_STATUS, status
> + ret
> +ENDPROC(rvv_enable)
> +
> +ENTRY(rvv_disable)
> + li status, SR_VS
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(rvv_disable)
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