linux-kernel - Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <b45b8cf8-de9d-7132-1a35-48deeb4b79d5@linaro.org>
Date:   Mon, 7 Nov 2022 09:28:07 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Liu Peibao <liupeibao@...ngson.cn>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Huacai Chen <chenhuacai@...nel.org>,
        WANG Xuerui <kernel@...0n.name>
Cc:     Jianmin Lv <lvjianmin@...ngson.cn>,
        Yinbo Zhu <zhuyinbo@...ngson.cn>, linux-mips@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for
 LoongArch CPU interrupt controller

On 07/11/2022 03:34, Liu Peibao wrote:

Add commit msg explaining what you are doing here (e.g. the hardware).

> Signed-off-by: Liu Peibao <liupeibao@...ngson.cn>
> ---
>  .../loongarch,cpu-interrupt-controller.yaml   | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
> new file mode 100644
> index 000000000000..30b742661a3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LoongArch CPU Interrupt Controller
> +
> +description: >
> +   On LoongArch the loongarch_cpu_irq_of_init() helper can be used to initialize
> +   the 14 CPU IRQs from a devicetree file and create a irq_domain for this IRQ
> +   controller.
> +
> +   With the irq_domain in place we can describe how the 14 IRQs are wired to the
> +   platforms internal interrupt controller cascade.

This should be the description of hardware, not Linux drivers.

> +
> +maintainers:
> +  - Liu Peibao <liupeibao@...ngson.cn>
> +
> +properties:
> +  compatible:
> +    const: loongarch,cpu-interrupt-controller

You have exactly one and only one type of CPU interrupt controller for
all your Loongarch designs? All current and all future? All?

> +
> +  '#interrupt-cells':

Best regards,
Krzysztof