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Message-ID: <alpine.DEB.2.22.394.2211081028180.714603@rhweight-WRK1>
Date: Tue, 8 Nov 2022 10:29:02 -0800 (PST)
From: matthew.gerlach@...ux.intel.com
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
cc: linux-fpga@...r.kernel.org, Xu Yilun <yilun.xu@...el.com>,
Wu Hao <hao.wu@...el.com>, Tom Rix <trix@...hat.com>,
Moritz Fischer <mdf@...nel.org>, Lee Jones <lee@...nel.org>,
Russ Weight <russell.h.weight@...el.com>,
Tianfei zhang <tianfei.zhang@...el.com>,
Mark Brown <broonie@...nel.org>,
Greg KH <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 09/12] intel-m10-bmc: Add regmap_indirect_cfg for Intel
FPGA IPs
On Tue, 8 Nov 2022, Ilpo Järvinen wrote:
> Create the regmap_indirect_cfg with offsets and commands for Intel FPGA
> IPs indirect register access.
This is a great improvement.
Reviewed-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
> ---
> include/linux/mfd/intel-m10-bmc.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h
> index ed920f76d3c8..1b907c1a176f 100644
> --- a/include/linux/mfd/intel-m10-bmc.h
> +++ b/include/linux/mfd/intel-m10-bmc.h
> @@ -15,6 +15,19 @@ enum m10bmc_type {
> M10_N5010,
> };
>
> +#define INTEL_M10_REGMAP_INDIRECT_CFG \
> + .cmd_offset = 0, \
> + .idle_cmd = 0, \
> + .read_cmd = BIT(0), \
> + .write_cmd = BIT(1), \
> + .ack_offset = 0, \
> + .ack_mask = BIT(2), \
> + .addr_offset = 0x4, \
> + .read_offset = 0x8, \
> + .write_offset = 0xc, \
> + .sleep_us = 1, \
> + .timeout_us = 10000
> +
> #define M10BMC_STAGING_SIZE 0x3800000
>
> /* Doorbell register fields */
> --
> 2.30.2
>
>
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