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Message-ID: <Y2vyz2OAp1xKedYc@zn.tnic>
Date: Wed, 9 Nov 2022 19:34:55 +0100
From: Borislav Petkov <bp@...en8.de>
To: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Cc: Andrew Cooper <Andrew.Cooper3@...rix.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"x86@...nel.org" <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Pavel Machek <pavel@....cz>,
"hdegoede@...hat.com" <hdegoede@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
"antonio.gomez.iglesias@...ux.intel.com"
<antonio.gomez.iglesias@...ux.intel.com>
Subject: Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG
enumeration
On Wed, Nov 09, 2022 at 09:37:20AM -0800, Pawan Gupta wrote:
> Looks like we need to restore this MSR too,
Why do we? Is that MSR read-only too or what is the reason for that one?
> and we can use existing X86_FEATURE_XMM2 to enumerate it.
Or 86_FEATURE_LFENCE_RDTSC.
> If SSBD is the only reason to restore MSR_AMD64_LS_CFG then we should
> be able to use X86_FEATURE_LS_CFG_SSBD for enumeration.
Yes, MSR_AMD64_LS_CFG is used in SSBD mitigations. For everything <= 0x12:
/* AMD Family 0xf - 0x12 */
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
On F14h it says here:
[ 0.278930] Speculative Store Bypass: Vulnerable
simply because it is not present there.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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