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Message-ID: <20221109173720.4ovtb2ao3vuuge43@desk>
Date: Wed, 9 Nov 2022 09:37:20 -0800
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: Andrew Cooper <Andrew.Cooper3@...rix.com>
Cc: Borislav Petkov <bp@...en8.de>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"x86@...nel.org" <x86@...nel.org>,
"H. Peter Anvin" <hpa@...or.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Pavel Machek <pavel@....cz>,
"hdegoede@...hat.com" <hdegoede@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
"antonio.gomez.iglesias@...ux.intel.com"
<antonio.gomez.iglesias@...ux.intel.com>
Subject: Re: [PATCH 2/3] x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG
enumeration
On Wed, Nov 09, 2022 at 12:45:58AM +0000, Andrew Cooper wrote:
>On 08/11/2022 23:10, Borislav Petkov wrote:
>> On Tue, Nov 08, 2022 at 02:51:41PM -0800, Pawan Gupta wrote:
>>> Looking at bsp_init_amd() this feature bit will only be set on AMD
>>> families 0x15-0x17. Andrew mentioned that the MSR LS_CFG is present on
>>> AMD family >= 0x10 && family <= 0x18.
>> Do you need to save that MSR on those families?
>>
>> Or do 0x15-0x18 suffice?
>>
>> Yes, 0x18 because that's Hygon and that does its own detection.
>>
>> So, do you need to save it on families 0x10-0x14?
>
>https://www.amd.com/system/files/documents/software-techniques-for-managing-speculation.pdf
>Mitigation G-2.
>
>The MSR exists on Fam 10/12/14/15/16/17, and in all cases the
>LFENCE_DISPATCH bit wants setting if not already set.
Isn't that a different MSR:
#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_F10H_DECFG 0xc0011029
#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
Looks like we need to restore this MSR too, and we can use existing
X86_FEATURE_XMM2 to enumerate it.
If SSBD is the only reason to restore MSR_AMD64_LS_CFG then we should be
able to use X86_FEATURE_LS_CFG_SSBD for enumeration.
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