linux-kernel - Re: [PATCH v5 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge

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Message-ID: <48094cb6-4662-d2ac-f5c8-371dd4cd5917@linaro.org>
Date:   Wed, 9 Nov 2022 10:09:58 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     "Havalige, Thippeswamy" <thippeswamy.havalige@....com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Cc:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "michals@...inx.com" <michals@...inx.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "Yeleswarapu, Nagaradhesh" <nagaradhesh.yeleswarapu@....com>,
        "Gogada, Bharat Kumar" <bharat.kumar.gogada@....com>
Subject: Re: [PATCH v5 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
 schemas of Xilinx NWL PCIe Root Port Bridge

On 09/11/2022 05:33, Havalige, Thippeswamy wrote:
> Hi,
> 
>>> +  dma-coherent:
>>> +    description: Optional, present if DMA operations are coherent
>>> +
>>> +  clocks:
>>> +    description: Optional, input clock specifier.
>>
>> This is a friendly reminder during the review process.
>>
>> It seems my previous comments were not fully addressed. Maybe my
>> feedback got lost between the quotes, maybe you just forgot to apply it.
>> Please go back to the previous discussion and either implement all requested
>> changes or keep discussing them.
>>
>> Hint: same comment as v3.
> 
> Sorry I assumed it only for 'Input' and not Optional.

Missed comment was maxItems: 1.

Best regards,
Krzysztof