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Message-ID: <6b282110-c9dc-c4ae-9003-1e75c3a0ff98@nvidia.com>
Date: Thu, 10 Nov 2022 13:18:30 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Steven Price <steven.price@....com>,
Thierry Reding <thierry.reding@...il.com>
Cc: Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
linux-kernel@...r.kernel.org, linux-pwm@...r.kernel.org,
linux-tegra@...r.kernel.org
Subject: Re: [PATCH] pwm: tegra: Fix 32 bit build
On 10/11/2022 11:45, Steven Price wrote:
> The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
> integer causing a build warning/error (and the value truncated):
>
> drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
> drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
> 148 | required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
> | ^~
>
> Explicitly cast to a u64 to ensure the correct result.
>
> Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
> Signed-off-by: Steven Price <steven.price@....com>
> ---
> drivers/pwm/pwm-tegra.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 6fc4b69a3ba7..249dc0193297 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -145,7 +145,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> * source clock rate as required_clk_rate, PWM controller will
> * be able to configure the requested period.
> */
> - required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
> + required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
> period_ns);
>
> if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
Thanks!
Reviewed-by: Jon Hunter <jonathanh@...dia.com>
Jon
--
nvpublic
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