linux-kernel - [RFC PATCH 2/2] pinctrl: sunxi: Add support for the Allwinner V5 pin controller

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Date:   Thu, 10 Nov 2022 01:42:55 +0000
From:   Andre Przywara <andre.przywara@....com>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Samuel Holland <samuel@...lland.org>
Cc:     Icenowy Zheng <uwu@...nowy.me>, linux-kernel@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev
Subject: [RFC PATCH 2/2] pinctrl: sunxi: Add support for the Allwinner V5 pin controller

The Allwinner V5 contains pins in all 10 possible pin banks.
Use the newly introduced DT based pinctrl driver to describe just the
generic pinctrl properties, so advertise the number of pins per bank
and the interrupt capabilities. The actual function/mux assignment is
taken from the devicetree.

Signed-off-by: Andre Przywara <andre.przywara@....com>
---
 drivers/pinctrl/sunxi/Kconfig            |  5 +++
 drivers/pinctrl/sunxi/Makefile           |  1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c | 52 ++++++++++++++++++++++++
 3 files changed, 58 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index a78fdbbdfc0c..6b8ea56c08fd 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -131,4 +131,9 @@ config PINCTRL_SUN50I_H616_R
 	default ARM64 && ARCH_SUNXI
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN8I_V5
+	bool "Support for the Allwinner V5 PIO"
+	default MACH_SUN8I
+	select PINCTRL_SUNXI
+
 endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index f5bad7a52951..5b289e18bd5a 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R)	+= pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_V3S)		+= pinctrl-sun8i-v3s.o
+obj-$(CONFIG_PINCTRL_SUN8I_V5)		+= pinctrl-sun8i-v5.o
 obj-$(CONFIG_PINCTRL_SUN20I_D1)		+= pinctrl-sun20i-d1.o
 obj-$(CONFIG_PINCTRL_SUN50I_H5)		+= pinctrl-sun50i-h5.o
 obj-$(CONFIG_PINCTRL_SUN50I_H6)		+= pinctrl-sun50i-h6.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c
new file mode 100644
index 000000000000..402b1c915e04
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner V5 SoC pinctrl driver.
+ *
+ * Copyright (C) 2022 Arm Ltd.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const unsigned int v5_irq_bank_map[] = { 0, 1, 5, 6, 7 };
+
+static const u8 v5_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
+/*       PA PB PC PD PE PF PG PH */
+        { 6, 6, 0, 0, 0, 6, 6, 6 };
+
+static const u8 v5_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
+/*        PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ */
+        { 16, 11, 17, 23, 18,  7, 14, 16, 17, 18 };
+
+static struct sunxi_pinctrl_desc v5_pinctrl_data = {
+	.irq_banks = ARRAY_SIZE(v5_irq_bank_map),
+	.irq_bank_map = v5_irq_bank_map,
+	.irq_read_needs_mux = true,
+	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int v5_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_dt_table_init(pdev, v5_nr_bank_pins,
+					   v5_irq_bank_muxes,
+					   &v5_pinctrl_data);
+}
+
+static const struct of_device_id v5_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-v5-pinctrl", },
+	{}
+};
+
+static struct platform_driver v5_pinctrl_driver = {
+	.probe	= v5_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-v5-pinctrl",
+		.of_match_table	= v5_pinctrl_match,
+	},
+};
+builtin_platform_driver(v5_pinctrl_driver);
-- 
2.35.5