linux-kernel - [RFC PATCH 0/2] pinctrl: sunxi: Introduce DT-based pinctrl builder

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 10 Nov 2022 01:42:53 +0000
From:   Andre Przywara <andre.przywara@....com>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Samuel Holland <samuel@...lland.org>
Cc:     Icenowy Zheng <uwu@...nowy.me>, linux-kernel@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev
Subject: [RFC PATCH 0/2] pinctrl: sunxi: Introduce DT-based pinctrl builder 

Hi,

since the dawn of time every Allwinner SoC dumped a rather large table
of data into the kernel, to describe the mapping between the pinctrl
function name and its mux value, for each pin.

This series introduces code that avoids that (for new SoCs), by instead
reading that information directly from the devicetree. We have per-pin
group nodes there anyway, and were just missing the mux value.

Compared to my previous effort almost exactly five years ago [1], this
new version drops the idea of describing the pinctrl data entirely in
the DT, instead it still relies on driver provided information for that.
That is more flexible, since it allows to introduce quirks and special
handling more cleanly, at the cost of still requiring a separate driver
file for each SoC. However this file is now very small, and can be
easily written and reviewed. All that is needed is the number of pins
per bank, plus information about each bank's IRQ capability.
Patch 2/2 shows an example, for the yet unsupported Allwinner V5 SoC.

On the DT side all that would be needed is *one* extra property per
pin group to announce the mux value:

	uart0_pb_pins: uart0-pb-pins {
		pins = "PB9", "PB10";
		function = "uart0";
		pinmux = <2>;
	};

The new code works by providing a function that builds the former
mapping table *at runtime*, by using both the driver provided
information, plus traversing all children of the pinctrl DT node, to
find all pin groups needed. This table looks the same as what we
hardcoded so far, so can easily be digested by the existing sunxi
pinctrl driver.

Please have a look and tell me whether this new approach has a better
future than my previous attempt.

Cheers,
Andre

[1] https://patchwork.ozlabs.org/project/linux-gpio/cover/20171113012523.2328-1-andre.przywara@arm.com/

Andre Przywara (2):
  pinctrl: sunxi: allow reading mux values from DT
  pinctrl: sunxi: Add support for the Allwinner V5 pin controller

 drivers/pinctrl/sunxi/Kconfig            |   5 +
 drivers/pinctrl/sunxi/Makefile           |   2 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c |  52 ++++
 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c | 355 +++++++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.h    |   8 +
 5 files changed, 422 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c

-- 
2.35.5