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Date: Fri, 11 Nov 2022 12:29:05 -0600
From: Rob Herring <robh@...nel.org>
To: Thippeswamy Havalige <thippeswamy.havalige@....com>
Cc: krzysztof.kozlowski@...aro.org, michals@...inx.com,
linux-pci@...r.kernel.org, bhelgaas@...gle.com,
bharat.kumar.gogada@....com, linux-kernel@...r.kernel.org,
robh+dt@...nel.org, devicetree@...r.kernel.org,
nagaradhesh.yeleswarapu@....com
Subject: Re: [PATCH v6 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
schemas of Xilinx NWL PCIe Root Port Bridge
On Fri, 11 Nov 2022 11:07:09 +0530, Thippeswamy Havalige wrote:
> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge
> dt binding.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
> ---
> changes in v6:
> Added maxItems to clocks property.
>
> .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------
> .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++
> 2 files changed, 149 insertions(+), 73 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>
Applied, thanks!
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