linux-kernel - Re: [PATCH v12 09/17] riscv: Add ptrace vector support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <c2de4e7a-9e17-4cc5-8891-baa5a8040e43@app.fastmail.com>
Date:   Mon, 14 Nov 2022 21:01:25 +0100
From:   "Arnd Bergmann" <arnd@...db.de>
To:     "Vineet Gupta" <vineetg@...osinc.com>,
        "Chris Stillson" <stillson@...osinc.com>
Cc:     "Greentime Hu" <greentime.hu@...ive.com>,
        "Vincent Chen" <vincent.chen@...ive.com>,
        "Paul Walmsley" <paul.walmsley@...ive.com>,
        "Palmer Dabbelt" <palmer@...belt.com>,
        "Anup Patel" <anup@...infault.org>,
        "Atish Patra" <atishp@...shpatra.org>, guoren <guoren@...nel.org>,
        "Conor.Dooley" <conor.dooley@...rochip.com>,
        "Andy Chiu" <andy.chiu@...ive.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        lkml <linux-kernel@...r.kernel.org>,
        Björn Töpel <bjorn@...nel.org>
Subject: Re: [PATCH v12 09/17] riscv: Add ptrace vector support

On Tue, Nov 8, 2022, at 02:38, Vineet Gupta wrote:
>>   static const struct user_regset_view riscv_user_native_view = {
>> diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
>> index c7b056af9ef0..5a5056c6a2a1 100644
>> --- a/include/uapi/linux/elf.h
>> +++ b/include/uapi/linux/elf.h
>> @@ -439,6 +439,7 @@ typedef struct elf64_shdr {
>>   #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */
>>   #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */
>>   #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */
>> +#define NT_RISCV_VECTOR	0x900		/* RISC-V vector registers */
>>   #define NT_LOONGARCH_CPUCFG	0xa00	/* LoongArch CPU config registers */
>>   #define NT_LOONGARCH_CSR	0xa01	/* LoongArch control and status registers */
>>   #define NT_LOONGARCH_LSX	0xa02	/* LoongArch Loongson SIMD Extension registers */
>
> I think we should break this one out as a seperate patch to be applied 
> independently, avoid merge conflicts (but this file doesn't change much 
> anyways. @Arnd or is it ok to carry with riscv change ?

I only saw this by accident, sorry for not replying earlier. Yes, please
keep it in this patch and merge it through the riscv tree.

       Arnd