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Message-Id: <cover.1668455932.git.pawan.kumar.gupta@linux.intel.com>
Date: Mon, 14 Nov 2022 12:06:14 -0800
From: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
To: "H. Peter Anvin" <hpa@...or.com>,
Thomas Gleixner <tglx@...utronix.de>, David.Kaplan@....com,
thomas.lendacky@....com, Borislav Petkov <bp@...en8.de>,
x86@...nel.org, hdegoede@...hat.com,
Dave Hansen <dave.hansen@...ux.intel.com>,
Andrew Cooper <Andrew.Cooper3@...rix.com>,
Pavel Machek <pavel@....cz>, Ingo Molnar <mingo@...hat.com>,
"Rafael J. Wysocki" <rafael@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
antonio.gomez.iglesias@...ux.intel.com
Subject: [PATCH v2 0/2] Check enumeration before MSR save/restore
v2:
- Dropped patch for X86_FEATURE_AMD64_LS_CFG, using X86_FEATURE_AMD64_LS_CFG_SSBD instead.
- Commit message updated.
v1: https://lore.kernel.org/lkml/cover.1663025154.git.pawan.kumar.gupta@linux.intel.com/
Hi,
This patchset is to fix the "unchecked MSR access error" [1] during S3
resume. Patch 1/3 adds a feature bit for MSR_IA32_TSX_CTRL.
Patch 2/3 adds a feature bit for MSR_AMD64_LS_CFG.
Patch 3/3 adds check for feature bit before adding any speculation
control MSR to the list of MSRs to save/restore.
[1] https://lore.kernel.org/lkml/20220906201743.436091-1-hdegoede@redhat.com/
Thanks,
Pawan
Pawan Gupta (2):
x86/tsx: Add feature bit for TSX control MSR support
x86/pm: Add enumeration check before spec MSRs save/restore setup
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/tsx.c | 30 +++++++++++++++---------------
arch/x86/power/cpu.c | 23 ++++++++++++++++-------
3 files changed, 32 insertions(+), 22 deletions(-)
--
2.37.3
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