linux-kernel - Re: [PATCH 17/22] phy: qcom-qmp-combo: merge USB and DP configurations

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Message-ID: <8802255c-16a9-1fb7-bbc5-d8e0d44a6f1f@linaro.org>
Date:   Mon, 14 Nov 2022 13:10:43 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Johan Hovold <johan@...nel.org>
Cc:     Johan Hovold <johan+linaro@...nel.org>,
        Vinod Koul <vkoul@...nel.org>, Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 17/22] phy: qcom-qmp-combo: merge USB and DP
 configurations

On 14/11/2022 11:54, Johan Hovold wrote:
> On Sat, Nov 12, 2022 at 10:43:14AM +0300, Dmitry Baryshkov wrote:
>> On 11/11/2022 11:56, Johan Hovold wrote:
>>> It does not really make any sense to keep separate configuration
>>> structures for the USB and DP parts of the same PHY so merge them.
>>>
>>> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
>>> ---
>>>    drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 182 +++++++---------------
>>>    1 file changed, 57 insertions(+), 125 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> index b27d1821116c..249912b75964 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>>> @@ -798,10 +798,7 @@ static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
>>>    
>>>    struct qmp_phy;
>>>    
>>> -/* struct qmp_phy_cfg - per-PHY initialization config */
>>>    struct qmp_phy_cfg {
>>> -	/* phy-type - PCIE/UFS/USB */
>>> -	unsigned int type;
>>>    	int lanes;
>>
>> int lanes doesn't really make sense here in my opinion. It should be
>> usb_lanes and dp_lanes.
> 
> It doesn't make much less sense than having it here currently do.
> 
> All of these USB-C PHYs are dual lane for bi-directional SS USB and
> quad lane for uni-directional DP (even if only CC1 orientation and lanes
> 2 and 3 are currently supported).

I was under impression that sdm845 has just a single lane for each of 
USB and DP. After rechecking the phy/next, I see that it was my mistake 
(quite logical, SS is two lanes, so the compliant PHY must have two 
lanes too).

I wander how/if 4-lane DP works. The only thing that we do is 
programming of the QSERDES_DP_PHY_PD_CTL register, however judging e.g. 
your 4-lane PCIe changes, one should probably also program the other two 
lanes. Maybe it is handled automatically inside the hardware.

> I should probably just drop the lanes parameter completely, either as a
> preparatory clean up or as follow-on one (e.g. also a bit depending on
> if there are other reasons for respinning a v2).

I think a follow up is enough, but let's get it. Having a single lanes=2 
field looks... strange.

-- 
With best wishes
Dmitry