linux-kernel - Re: [External] : [RFC PATCH v2 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2

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Date:   Mon, 14 Nov 2022 12:59:30 +0000
From:   John Garry <john.g.garry@...cle.com>
To:     Jing Zhang <renyu.zj@...ux.alibaba.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        John Garry <john.garry@...wei.com>,
        Will Deacon <will@...nel.org>,
        James Clark <james.clark@....com>,
        Mike Leach <mike.leach@...aro.org>,
        Leo Yan <leo.yan@...aro.org>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Andrew Kilroy <andrew.kilroy@....com>,
        Shuai Xue <xueshuai@...ux.alibaba.com>,
        Zhuo Song <zhuo.song@...ux.alibaba.com>
Subject: Re: [External] : [RFC PATCH v2 1/6] perf vendor events arm64: Add
 topdown L1 metrics for neoverse-n2

On 14/11/2022 07:41, Jing Zhang wrote:
> The calculation formula of topdown L1 is from the document:
> https://urldefense.com/v3/__https://documentation-service.arm.com/static/60250c7395978b529036da86?token=__;!!ACWV5N9M2RV99hQ!Ll-Jgvfs0LitTCU-hC6i6BKBVJfhke-pbQq2VoO-gmuSAcglQ3ZqMVMd2r0An_5a3ZDPYmn8zXuCrpUbehwnLHplVQ$  

So since this is a from "standard" document, did you consider putting 
these as an arch std event? I think arch std events would work for 
metrics, like they do for regular events.

> 
> However, due to the wrong count of stall_slot and stall_slot_frontend
> in neoverse-n2, the real stall_slot and real stall_slot_frontend need
> to subtract cpu_cycles, so when calculating the topdownL1 metrics,
> stall_slot and stall_slot_frontend are corrected.

Is there a reference to this? It would be indeed useful to pass a link 
to the n2 doc as these metrics are not part of the arm64 arm. At least I 
assume that they are not there.

> 
> Since neoverse-n2 does not yet support topdown L2, metricgroups such
> as Cache, TLB, Branch, InstructionsMix, and PEutilization will be
> added to further analysis of performance bottlenecks in the following
> patches.
> 


Thanks,
John