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Message-ID: <5ff80fe0-eb23-9db0-ab75-189da5977901@linaro.org>
Date: Wed, 16 Nov 2022 09:10:44 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
agross@...nel.org, andersson@...nel.org
Cc: konrad.dybcio@...ainline.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sc8280xp/sa8540p: add SoundWire and
LPASS
On 15/11/2022 18:02, Srinivas Kandagatla wrote:
> Add LPASS Codecs along with SoundWire controller for TX, RX, WSA and VA macros
> along with LPASS LPI pinctrl node.
>
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 324 +++++++++++++++++++++++++
> 1 file changed, 324 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index e3cdd8bccb0c..a87d58bee1e0 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/sound/qcom,q6afe.h>
> #include <dt-bindings/thermal/thermal.h>
> #include <dt-bindings/soc/qcom,gpr.h>
>
> @@ -1115,6 +1116,9 @@ usb_2_ssphy1: phy@...1e00 {
> };
> };
>
> + sound: sound {
> + };
sound node is not part of SoC.
> +
> remoteproc_adsp: remoteproc@...0000 {
> compatible = "qcom,sc8280xp-adsp-pas";
> reg = <0 0x03000000 0 0x100>;
> @@ -1195,6 +1199,326 @@ q6prmcc: cc {
> };
> };
>
> + rxmacro: rxmacro@...0000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&rx_swr_active>;
> + compatible = "qcom,sc8280xp-lpass-rx-macro";
> + reg = <0 0x3200000 0 0x1000>;
> + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&vamacro>;
> +
> + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
> +
> + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + assigned-clock-rates = <19200000>, <19200000>;
> +
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + clock-output-names = "mclk";
> + #sound-dai-cells = <1>;
> + };
> +
> + /* RX */
> + swr1: soundwire-controller@...0000 {
> + reg = <0 0x3210000 0 0x2000>;
> + compatible = "qcom,soundwire-v1.6.0";
> + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&rxmacro>;
> + clock-names = "iface";
> + label = "RX";
> + qcom,din-ports = <0>;
> + qcom,dout-ports = <5>;
> +
> + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
> + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
> + qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
> + qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
> + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
> + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
> + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
> + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
> + #sound-dai-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + txmacro: txmacro@...0000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&tx_swr_active>;
> + compatible = "qcom,sc8280xp-lpass-tx-macro";
> + reg = <0 0x3220000 0 0x1000>;
> + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
Align the opening <
> + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&vamacro>;
> +
> + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
> + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + assigned-clock-rates = <19200000>, <19200000>;
> +
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + clock-output-names = "mclk";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #sound-dai-cells = <1>;
> + };
> +
> + /* TX */
> + swr2: soundwire-controller@...0000 {
> + reg = <0 0x3330000 0 0x2000>;
> + compatible = "qcom,soundwire-v1.6.0";
> + interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "core", "wake";
> +
> + clocks = <&vamacro>;
> + clock-names = "iface";
> + label = "TX";
> +
> + qcom,din-ports = <4>;
> + qcom,dout-ports = <0>;
> + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
> + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
> + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
> + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-word-length = /bits/ 8 <0xFF 0x00 0xFF 0xFF>;
> + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
> + qcom,port-offset = <1>;
> + #sound-dai-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + wsamacro: codec@...0000 {
Order nodes by unit address.
> + compatible = "qcom,sc8280xp-lpass-wsa-macro";
> + reg = <0 0x03240000 0 0x1000>;
> + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&vamacro>;
> + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
> +
> + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + assigned-clock-rates = <19200000>, <19200000>;
> +
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + clock-output-names = "mclk";
> + #sound-dai-cells = <1>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&wsa_swr_active>;
> + };
> +
> + /* WSA */
> + swr0: soundwire-controller@...0000 {
> + reg = <0 0x03250000 0 0x2000>;
> + compatible = "qcom,soundwire-v1.6.0";
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&wsamacro>;
> + clock-names = "iface";
> +
> + qcom,din-ports = <2>;
> + qcom,dout-ports = <6>;
> +
> + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
> + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
> + qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
> + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>;
> + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>;
> + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>;
> + qcom,port-offset = <1>;
> + #sound-dai-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + vamacro: codec@...0000 {
> + compatible = "qcom,sc8280xp-lpass-va-macro";
> + reg = <0 0x03370000 0 0x1000>;
> + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> +
> + clock-names = "mclk", "npl", "macro", "dcodec";
> + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + assigned-clock-rates = <19200000>;
> +
> + #clock-cells = <0>;
> + clock-frequency = <19200000>;
> + clock-output-names = "fsgen";
> + #sound-dai-cells = <1>;
> + };
> +
> + lpass_tlmm: pinctrl@...0000 {
> + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
> + reg = <0 0x33c0000 0x0 0x20000>,
> + <0 0x3550000 0x0 0x10000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&lpass_tlmm 0 0 18>;
> +
> + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> + clock-names = "core", "audio";
> +
> + wsa_swr_active: wsa-swr-active-pins {
There is no way this passes bindings test. state suffix.
> + clk {
pins suffix
> + pins = "gpio10";
> + function = "wsa_swr_clk";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-disable;
> + };
> +
> + data {
> + pins = "gpio11";
> + function = "wsa_swr_data";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-bus-hold;
> +
> + };
> + };
> +
> + tx_swr_active: tx_swr-active-pins {
> + clk {
> + pins = "gpio0";
> + function = "swr_tx_clk";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-disable;
> + };
> +
> + data {
> + pins = "gpio1", "gpio2";
> + function = "swr_tx_data";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-bus-hold;
> + };
> + };
> +
> + rx_swr_active: rx_swr-active-pins {
> + clk {
> + pins = "gpio3";
> + function = "swr_rx_clk";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-disable;
> + };
> +
> + data {
> + pins = "gpio4", "gpio5";
> + function = "swr_rx_data";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-bus-hold;
> + };
> + };
> +
> + wsa2_swr_active: wsa2-swr-active-pins {
> + clk {
> + pins = "gpio15";
> + function = "wsa2_swr_clk";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-disable;
> + };
> +
> + data {
> + pins = "gpio16";
> + function = "wsa2_swr_data";
> + drive-strength = <2>;
> + slew-rate = <1>;
> + bias-bus-hold;
> + };
> + };
> +
> + dmic01_active: dmic01-active-pins {
> + clk {
> + pins = "gpio6";
> + function = "dmic1_clk";
> + drive-strength = <8>;
> + output-high;
> + };
Blank line
> + data {
> + pins = "gpio7";
> + function = "dmic1_data";
> + drive-strength = <8>;
> + input-enable;
> + };
> + };
> +
> + dmic01_sleep: dmic01-sleep-pins {
> + clk {
> + pins = "gpio6";
> + function = "dmic1_clk";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> +
> + data {
> + pins = "gpio7";
> + function = "dmic1_data";
> + drive-strength = <2>;
> + pull-down;
> + input-enable;
> + };
> + };
> +
> + dmic02_active: dmic02-active-pins {
> + clk {
> + pins = "gpio8";
> + function = "dmic2_clk";
> + drive-strength = <8>;
> + output-high;
> + };
Blank line
> + data {
> + pins = "gpio9";
> + function = "dmic2_data";
> + drive-strength = <8>;
> + input-enable;
> + };
> + };
> +
Best regards,
Krzysztof
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