linux-kernel - Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a

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Message-ID: <166904347234.110206.17589420162620604946.b4-ty@microchip.com>
Date:   Mon, 21 Nov 2022 17:11:22 +0200
From:   Tudor Ambarus <tudor.ambarus@...rochip.com>
To:     <linux-kernel@...r.kernel.org>, <linux-mtd@...ts.infradead.org>,
        <richard@....at>, <vigneshr@...com>, <pratyush@...nel.org>,
        <michael@...le.cc>, <farbere@...zon.com>,
        <miquel.raynal@...tlin.com>
CC:     Tudor Ambarus <tudor.ambarus@...rochip.com>, <talel@...zon.com>,
        <shellykz@...zon.com>, <hhhawa@...zon.com>, <jonnyc@...zon.com>,
        <itamark@...zon.com>, <dkl@...zon.com>, <amitlavi@...zon.com>,
        <hanochu@...zon.com>
Subject: Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a

On Thu, 20 Oct 2022 09:20:58 +0000, Eliav Farber wrote:
> mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on MT25QU256ABA8ESF-0SIT.
> 
> [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
> 
> [...]

Applied to spi-nor/next, thanks!

[1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
      https://git.kernel.org/mtd/c/bcc0c61e6134

Best regards,
-- 
Tudor Ambarus <tudor.ambarus@...rochip.com>