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Message-ID: <126b0517-2f10-4a31-e76d-8afb1aff6275@starfivetech.com>
Date: Tue, 22 Nov 2022 09:45:47 +0800
From: Hal Feng <hal.feng@...rfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Conor Dooley <conor@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
"Michael Turquette" <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 09/14] dt-bindings: clock: Add StarFive JH7110 system
clock and reset generator
On Sat, 19 Nov 2022 00:50:41 +0800, Emil Renner Berthing wrote:
> On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@...rfivetech.com> wrote:
> > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> > new file mode 100644
> > index 000000000000..a8cafbc0afe2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> > @@ -0,0 +1,80 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 System Clock and Reset Generator
> > +
> > +maintainers:
> > + - Emil Renner Berthing <kernel@...il.dk>
> > +
> > +properties:
> > + compatible:
> > + const: starfive,jh7110-syscrg
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Main Oscillator (24 MHz)
> > + - description: RMII reference clock
> > + - description: RGMII RX clock
> > + - description: I2S TX bit clock
> > + - description: I2S TX left/right clock
> > + - description: I2S RX bit clock
> > + - description: I2S RX left/right clock
> > + - description: TDM
> > + - description: mclk
>
> Maybe you could ask your colleagues for a better description of these clocks.
OK, I will improve the description.
Best regards,
Hal
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