linux-kernel - Re: [PATCH v3 4/4] x86/of: Add support for boot time interrupt delivery mode configuration

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e5028335-97f9-dd88-09e9-9036b55e7642@maxlinear.com>
Date:   Tue, 22 Nov 2022 09:45:29 +0000
From:   Rahul Tanwar <rtanwar@...linear.com>
To:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
CC:     "bigeasy@...utronix.de" <bigeasy@...utronix.de>,
        "robh@...nel.org" <robh@...nel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>,
        "hpa@...or.com" <hpa@...or.com>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@...linear.com>
Subject: Re: [PATCH v3 4/4] x86/of: Add support for boot time interrupt
 delivery mode configuration

On 22/11/2022 5:14 pm, Andy Shevchenko wrote:
> This email was sent from outside of MaxLinear.
> 
> 
> On Tue, Nov 22, 2022 at 03:39:10PM +0800, Rahul Tanwar wrote:
>> Presently, init/boot time interrupt delivery mode is enumerated
>> only for ACPI enabled systems by parsing MADT table or for older
>> systems by parsing MP table. But for OF based x86 systems, it is
>> assumed & hardcoded to legacy PIC mode. This is a bug for
>> platforms which are OF based but do not use 8259 compliant legacy
>> PIC interrupt controller. Such platforms can not even boot because
>> of this bug/hardcoding.
>>
>> Fix this bug by adding support for configuration of init time
>> interrupt delivery mode for x86 OF based systems by introducing a
>> new optional boolean property 'intel,virtual-wire-mode' for
>> interrupt-controller node of local APIC. This property emulates
>> IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer
>> structure.
>>
>> Defaults to legacy PIC mode if absent. Configures it to virtual
>> wire compatibility mode if present.
> 
>> Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC")
> 
> If it was never working, there is nothing to fix.
> OTOH, without Cc: stable@ this is up to stable maintainers to
> backport.
>

Agree, will remove fixes tag..


> 
>> Suggested-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> 
> I definitely haven't suggested this fix.
> 

Yes, i copy pasted to entire series. I will remove it from this patch.

> ...
> 
> The code looks good to me.
>

Thanks.

Regards,
Rahul


> --
> With Best Regards,
> Andy Shevchenko
> 
> 
>