linux-kernel - RE: [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support

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Date:   Thu, 24 Nov 2022 03:10:50 +0000
From:   "Tian, Kevin" <kevin.tian@...el.com>
To:     Thomas Gleixner <tglx@...utronix.de>,
        LKML <linux-kernel@...r.kernel.org>
CC:     "x86@...nel.org" <x86@...nel.org>, Joerg Roedel <joro@...tes.org>,
        "Will Deacon" <will@...nel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        "Lorenzo Pieralisi" <lorenzo.pieralisi@....com>,
        Marc Zyngier <maz@...nel.org>,
        "Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
        Jason Gunthorpe <jgg@...lanox.com>,
        "Jiang, Dave" <dave.jiang@...el.com>,
        Alex Williamson <alex.williamson@...hat.com>,
        "Williams, Dan J" <dan.j.williams@...el.com>,
        Logan Gunthorpe <logang@...tatee.com>,
        "Raj, Ashok" <ashok.raj@...el.com>, Jon Mason <jdmason@...zu.us>,
        Allen Hubbe <allenbh@...il.com>
Subject: RE: [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store)
 support

> From: Thomas Gleixner <tglx@...utronix.de>
> Sent: Monday, November 21, 2022 10:38 PM
> 
> The IMS domains have a few constraints:
> 
>   - The index space is managed by the core code.
> 
>     Device memory based IMS provides a storage array with a fixed size
>     which obviously requires an index. But there is no association between
>     index and functionality so the core can randomly allocate an index in
>     the array.
> 
>     Queue memory based IMS does not have the concept of an index as the
>     storage is somewhere in memory. In that case the index is purely
>     software based to keep track of the allocations.

'Queue' could be a HW queue or SW queue. Is it clearer to just use
'system memory based IMS" here?

and for a GPU it is probably just a gfx context to store IMS content, w/o
a queue concept.