linux-kernel - [IP REVIEW PATCH 0/3] Add support for Lane Margining at Receiver

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Message-ID: <20221124083510.3008139-1-mmaddireddy@nvidia.com>
Date:   Thu, 24 Nov 2022 14:05:07 +0530
From:   Manikanta Maddireddy <mmaddireddy@...dia.com>
To:     <vkoul@...nel.org>, <kishon@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <thierry.reding@...il.com>,
        <jonathanh@...dia.com>, <vidyas@...dia.com>
CC:     <linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <bhelgaas@...gle.com>,
        <lpieralisi@...nel.org>, <nkristam@...dia.com>,
        Manikanta Maddireddy <mmaddireddy@...dia.com>
Subject: [IP REVIEW PATCH 0/3] Add support for Lane Margining at Receiver

Tegra234 supports Lane Margining at Receiver feature. However, this
requires programming of per lane PIPE2UPHY hardware instance to relay
the lane margin control and margin status information between PCIe
controller and UPHY modules. This series adds this support in PIPE2UPHY
driver.

Manikanta Maddireddy (3):
  phy: tegra: p2u: Add lane margin support
  dts: soc: t234: Add uphy lane number and intr in p2u nodes
  dt-bindings: PHY: P2U: Add PCIe lane margining support

 .../bindings/phy/phy-tegra194-p2u.yaml        |  50 ++++
 arch/arm64/boot/dts/nvidia/tegra234.dtsi      | 120 ++++++++
 drivers/phy/tegra/phy-tegra194-p2u.c          | 274 ++++++++++++++++++
 3 files changed, 444 insertions(+)

-- 
2.25.1